Power saving operation of an apparatus with a cache memory

• US 20070055901A1
• Filed: 08/30/2004
• Published: 03/08/2007
• Est. Priority Date: 09/16/2003
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Der Heijden, Gerardus Wilhelmus
• Granted Patent: US 7,523,331 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3225 of memory devices

Abstract

An apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16). In a normal mode the cache memory (16) is used to cache a part of data and /or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18). The circuit is able to switch to a low power operating mode. Upon the switch an interrupt program for executing a function during operation in the low power operating mode is loaded into the cache memory (16) from the main memory (18). Power supply to the main memory (18) is then switched off, but keeping at least a part of the cache memory (16) continuous to receive power supply. This part ensures that the program of instructions for executing the function is available to the instruction processing circuit. The program is executed from said at least part of the cache memory (16) in the low power operating mode.

Claims

1. An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising:

an instruction processing circuit (14);

a main memory (18) for providing instructions for the instruction processing circuit (14) during execution by the instruction processing circuit (14);

a cache memory (16) coupled between the instruction processing circuit (14) and the main memory (18), operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18);

low power operating mode activating circuit (10, 12, 14), arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory (18), but excluding at least part of the cache memory (16), the low power mode activating circuit (10, 12, 14) being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory (16) before switching to the low power operating mode.

2. An apparatus according to claim 1, wherein the cache memory (16) is switchable to a locked state, wherein the cache memory (16) is disabled from discarding locked information, the low power operating mode activating circuit (10, 12, 14) being arranged to switch the cache memory (16) to the locked state so as to lock the program of instructions for executing the function in the cache memory (16).

3. An apparatus according to claim 1, wherein the low power operating mode activating circuit (10, 12, 14) is arranged to load, upon switching to the low power operating mode, all data into the cache memory (16) that will be addressed with addresses in main memory (18) by the program of instructions for executing the function.

4. An apparatus according to claim 1, wherein said program of instructions for executing a function in the low power operating mode is an interrupt program, the apparatus comprising an interrupt circuit (19) for triggering the instruction processing circuit to execute the interrupt program at selected times during operation in the low power operating mode.

5. A method of operating an apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16), the method comprising:

using the cache memory (16) and the main memory (18) in a normal operating mode, to cache in cache memory (16) a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18);

switching to a low power operating mode, by

loading a program of instructions for executing a function during operation in the low power operating mode into the cache memory

deactivating the main memory (18) to reduce power consumption, but keeping active at least a part of the cache memory (16), that is needed for retrieving the program of instructions for executing the function;

executing the program of instructions in the low power operating mode from said at least part of the cache memory (16).