Integrated device

• US 20070055917A1
• Filed: 09/06/2006
• Published: 03/08/2007
• Est. Priority Date: 09/07/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kashiwaya, Motofumi
• Granted Patent: US 8,145,851 B2
• Time in Patent Office: Days
• US Class Current: 714/49
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Claims

1. An integrated device comprising:

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

wherein

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects.

2. An integrated device as set forth in claim 1, wherein

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the region of the memory macro therebetween;

memory macros of the plurality of memory systems are arranged in parallel in a second direction, the second direction substantially perpendicularly intersecting a first direction, the first direction being a direction connecting the processing module and the memory interface;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnect being arranged in the first direction and the second direction so as to shape a matrix form in the region of the memory macros; and

the data interconnects are formed by private interconnects for at least the interconnects in the second direction.

3. An integrated device as set forth in claim 2, wherein

If a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

If a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

4. An integrated device as set forth in claim 2, further comprising:

a sub processing module arranged at least one side of the region of the plurality of memory macros in the second direction, the sub processing modules being able to selectively access at least one of predetermined memory bank of the plurality of memory macros in the second direction; and

the data interconnects in the second direction able to be used as a second direction transfer mode.

5. An integrated device as set forth in claim 1, wherein

the device further includes a plurality of dies arranged at predetermined intervals;

and

the processing modules and the memory systems are formed at different dies.

6. An integrated device comprising:

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals, wherein

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies; and

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects.

7. An integrated device as set forth in claim 6, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.

8. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the plurality of access clusters are connected by buses;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects.

9. An integrated device as set forth in claim 8, wherein, in each access cluster,

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the region of the memory macro therebetween;

memory macros of the plurality of memory systems are arranged in parallel in a second direction, the second direction substantially perpendicularly intersecting a first direction, the first direction being a direction connecting the processing module and the memory interface;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnect being arranged in the first direction and the second direction so as to shape a matrix form in the region of the memory macros; and

the plurality of access clusters are arranged in parallel in the second direction, and memory banks corresponding to the matrix arrangement of the plurality of memory macros are connected to each other by buses arranged in the second direction;

the data interconnects are formed by private interconnects for at least the interconnects in the second direction.

10. An integrated device as set forth in claim 9, wherein

If a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

If a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

11. An integrated device as set forth in claim 10, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

12. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals;

each memory system includes

a memory macro including a plurality of memory banks and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies,;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the plurality of access clusters are connected by buses.

13. An integrated device as set forth in claim 12, wherein

the plurality of dies are arranged to face each other,

a first die formed with the processing module includes the input/output port formed at its center;

and

a second die formed with the memory system is formed with the memory interface at its center.

14. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects; and

the plurality of access clusters are symmetrically arranged in a predetermined direction via the interfaces and share memory interfaces arranged at corresponding positions with each other.

15. An integrated device as set forth in claim 14, wherein, in each access cluster,

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the region of the memory macro therebetween;

memory macros of the plurality of memory systems are arranged in parallel in a second direction, the second direction substantially perpendicularly intersecting a first direction, the first direction being a direction connecting the processing module and the memory interface;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnect being arranged in the first direction and the second direction so as to shape a matrix form in the region of the memory macros; and

the data interconnects are formed by private interconnects for at least the interconnects in the second direction; and

the plurality of access clusters are arranged symmetrically across the interface in the first direction and share memory interfaces arranged at positions corresponding with each other.

16. An integrated device as set forth in claim 15, wherein

If a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

If a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

17. An integrated device as set forth in claim 16, wherein,

when the data interconnects are formed by private interconnects extending from the processing module up to the memory interface, the interconnects with respect to memory systems on the side exceeding the memory interface in the first direction are formed by a common interconnect;

and

the memory interface selectively transfers the data transferred through the private interconnects to the common interconnect interconnected in the first direction on the side exceeding the memory interface.

18. An integrated device as set forth in claim 17, wherein the memory interface selectively transfers the data transferred through the common interconnect to the private interconnects in the first direction on the side exceeding the memory interface.

19. An integrated device as set forth in claim 15, wherein

the shared memory interface includes an arbitration portion arbitrating the access to the desired memory system;

and

the arbitration portion selectively issues commands transmitted from the plurality of processing modules to the bank of at least one memory system between the memory system on the first side and the memory system on the second side arranged in the first direction sandwiching the memory interface therebetween.

20. An integrated device as set forth in claim 19, wherein the arbitration portion able to issue a plurality of commands to at least one of the memory system on the first side and the memory system on the second side.

21. An integrated device as set forth in claim 15, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

22. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals,

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the plurality of access clusters are symmetrically arranged in a predetermined direction via the interfaces and share memory interfaces arranged at corresponding positions with each other.

23. An integrated device as set forth in claim 22, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.

24. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects;

the plurality of access clusters are symmetrically arranged in a first direction via the interfaces and share memory interfaces arranged at corresponding positions with each other;

remaining access clusters are arranged in parallel in a second direction substantially perpendicularly intersecting the first direction; and

memory banks corresponding to the matrix arrangement of the plurality of memory macros are connected to each other by buses arranged in the second direction.

25. An integrated device as set forth in claim 24, wherein, in each access cluster;

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the region of the memory macro therebetween;

memory macros of the plurality of memory systems are arranged in parallel in a second direction, the second direction substantially perpendicularly intersecting a first direction, the first direction being a direction connecting the processing module and the memory interface;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnect being arranged in the first direction and the second direction so as to shape a matrix form in the region of the memory macros; and

the data interconnects are formed by private interconnects for at least the interconnects in the second direction; and

the plurality of access clusters are arranged symmetrically across the interface in the first direction and share memory interfaces arranged at positions corresponding with each other; and

remaining access clusters are arranged in parallel in a second direction, and memory banks corresponding to the matrix arrangement of the plurality of memory macros are connected to each other by buses arranged in the second direction.

26. An integrated device as set forth in claim 25, wherein,

when the data interconnects are formed by private interconnects extending from the processing module up to the memory interface, the interconnects with respect to memory systems on the side exceeding the memory interface in the first direction are formed by a common interconnect;

and

the memory interface selectively transfers the data transferred through the private interconnects to the common interconnect interconnected in the first direction on the side exceeding the memory interface.

27. An integrated device as set forth in claim 26, wherein the memory interface selectively transfers the data transferred through the common interconnect to the private interconnects in the first direction on the side exceeding the memory interface.

28. An integrated device as set forth in claim 25, wherein

the shared memory interface includes an arbitration portion arbitrating the access to the desired memory system;

and

the arbitration portion selectively issues commands transmitted from the plurality of processing modules to the bank of at least one memory system between the memory system on the first side and the memory system on the second side arranged in the first direction sandwiching the memory interface therebetween.

29. An integrated device as set forth in claim 28, wherein the arbitration portion able to issue a plurality of commands to at least one of the memory system on the first side and the memory system on the second side.

30. An integrated device as set forth in claim 25, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

31. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals;

each memory system includes

a memory macro including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects;

the plurality of access clusters are symmetrically arranged in the first direction via the interfaces and share memory interfaces arranged at corresponding positions with each other;

remaining access clusters are arranged in parallel in a second direction substantially perpendicularly intersecting the first direction; and

memory banks corresponding to the matrix arrangement of the plurality of memory macros are connected to each other by buses arranged in the second direction.

32. An integrated device as set forth in claim 31, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.

33. An integrated device comprising:

a memory system including a plurality of unit memories able to be independently accessed;

at least one processing module able to access the plurality of unit memories;

interconnects of a basic route shared by the plurality of unit memories for selectively accessing to one arbitrary unit memory of the plurality of unit memories by the processing module; and

interconnects of a bypass route for accessing to at least one predetermined unit memory of the plurality of unit memories by the processing module.

34. An integrated device as set forth in claim 33, wherein the bypass route is utilized when shorter than a route length through the basic route.

35. An integrated device as set forth in claim 33, including:

a planar configuration formed by

a memory layer at which the plurality of unit memories are arranged; and

an interconnect layer including interconnects in a stacking direction connecting the memory layer and either the basic route, the bypass route, or combination thereof.

36. An integrated device as set forth in claim 33, including:

a planar configuration formed by

a processing module layer in which the processing module is arranged; and

an interconnect layer including interconnects in a stacking direction connecting the processing module layer and either the basic route, the bypass route, or combination thereof.

37. An integrated device as set forth in claim 35, wherein the interconnects of the bypass route include interconnects in the stacking direction connected to the middle of the basic route.

38. An integrated device as set forth in claim 35, wherein the interconnect layer includes interconnects of a planar direction forming part of either the basic route, the bypass route, or combination thereof.

39. An integrated device as set forth in claim 38, wherein the interconnects of a planar direction form part of interconnects of a matrix shape formed in the interconnect layer.

40. An integrated device as set forth in claim 33, including:

a plurality of planar configurations arranged in parallel; and

interconnects of a normal direction connecting the plurality of planar configurations;

wherein the plurality of planar configurations includes

a processing module planar configuration in which the processing module is arranged; and

a memory planar configuration in which the plurality of unit memories are arranged; and

the interconnects of a normal direction includes interconnects forming part of the basic route and the bypass route.

41. An integrated device as set forth in claim 33, including

a plurality of processing modules;

wherein which access route of the basic route and the bypass route is used is determined based on a relative position between the accessing processing module and the unit memory to be accessed.