Transflective liquid crystal display device and method of fabricating the same

• US 20070058116A1
• Filed: 03/10/2006
• Published: 03/15/2007
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lee, Jung, Yang, Joon
• Granted Patent: US 7,714,963 B2
• Time in Patent Office: Days
• US Class Current: 349/114
• CPC Class Codes: G02F 1/133371 Cells with varying thickness of the liquid crystal layer
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2203/02 reflective

Abstract

An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line; a first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole; and a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode.

Claims

1. An array substrate for a transflective liquid crystal display device, comprising:

a substrate;

a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;

a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line

a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area;

a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole; and

a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode.

2. The array substrate according to claim 1, further comprising a storage capacitor electrically connected to the reflective plate, wherein the storage capacitor includes a first storage electrode that is a portion of the gate line, a portion of the gate insulating layer on the first storage electrode and a second storage electrode on the gate insulating layer.

3. The array substrate according to claim 2, wherein the first passivation layer has a storage contact hole exposing the second storage electrode, and the reflective plate is electrically connected to the second storage electrode through the storage contact hole.

4. The array substrate according to claim 3, further comprising a storage terminal of a transparent conductive material between the reflective plate and the second storage electrode.

5. The array substrate according to claim 4, wherein the storage terminal is formed of the same layer as the pixel electrode.

6. The array substrate according to claim 1, wherein the pixel electrode is formed on a bottom and a sidewall of the through hole, and wherein the reflective plate electrically contacts the pixel electrode on the sidewall of the through hole and exposes the pixel electrode on the bottom of the through hole.

7. The array substrate according to claim 1, further comprising a drain terminal of a transparent conductive material between the reflective plate and the drain electrode, wherein the reflective plate is electrically connected to the drain electrode through the drain terminal.

8. The array substrate according to claim 7, wherein the drain terminal is formed of the same layer as the pixel electrode.

9. The array substrate according to claim 1, further comprising a second passivation layer of an inorganic insulating material between the thin film transistor and the first passivation layer, wherein the second passivation layer has the drain contact hole exposing the drain electrode.

10. The array substrate according to claim 9, further comprising a third passivation layer of an inorganic insulating material between the first passivation layer and the reflective plate, wherein the third passivation layer has the drain contact hole exposing the drain electrode.

11. The array substrate according to claim 1, further comprising a gate pad at one end of the gate line and a data pad at one end of the data line.

12. The array substrate according to claim 11, further comprising a gate pad terminal on the gate pad and a data pad terminal on the data pad, wherein the gate pad terminal and the data pad terminal are formed of a transparent conductive material.

13. The array substrate according to claim 12, wherein gate pad terminal and the data pad terminal is formed of the same layer as the pixel electrode.

14. The array substrate according to claim 1, wherein the first passivation layer is formed of an organic insulating material and has an uneven top surface.

15. The array substrate according to claim 14, wherein the reflective plate has an embossed shape corresponding to the uneven top surface of the first passivation layer.

16. The array substrate according to claim 1, wherein the thin film transistor includes a gate electrode, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer over the gate electrode, an ohmic contact layer on the active layer, a source electrode on the ohmic contact layer, the drain electrode spaced apart from the source electrode.

17. A method of fabricating an array substrate for a transflective liquid crystal display device, comprising:

forming a gate line and a data line on a substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;

forming a gate insulating layer between the gate line and the data line;

forming a thin film transistor connected to the gate line and the data line;

forming a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the gate insulating layer on the substrate in the transmissive area;

forming a second passivation layer on the first passivation layer;

forming a first photoresist pattern on the second passivation layer, the first photoresist pattern exposing the drain contact hole and the through hole;

etching the second passivation layer and the gate insulating layer using the first photoresist pattern as an etch mask such that the drain electrode is exposed through the drain contact hole and the substrate is exposed through the through hole;

forming a transparent conductive material layer on the first photoresist pattern;

forming a first photoresist layer on the transparent conductive material layer;

anisotropically removing the first photoresist layer to form a second photoresist pattern on the transparent conductive material layer in the drain contact hole and the through hole;

etching the transparent conductive material layer using the second photoresist pattern as an etch mask to form a drain terminal in the drain contact hole and a pixel electrode in the through hole;

removing the first and second photoresist patterns; and

forming a reflective plate on the drain terminal and the pixel electrode, the reflective plate contacting the drain terminal and the pixel electrode.

18. The method according to claim 17, further comprising forming a third passivation layer between the thin film transistor and the first passivation layer.

19. The method according to claim 17, wherein the first passivation layer is formed of an organic insulating material, and the second and third passivation layers include an inorganic insulating material.

20. The method according to claim 19, wherein the forming the first passivation layer includes exposing and developing the organic insulating material having a photosensitivity using a mask having transmissive region, a blocking region and a half-transmissive region such that a transmittance of the half-transmissive region is greater than a transmittance of the blocking region and smaller than a transmittance of the transmissive region to form an uneven top surface of the first passivation layer.

21. The method according to claim 17, further comprising forming a storage electrode on the gate insulating layer over the gate line, and forming a data pad at one end of the data line.

22. The method according to claim 21, wherein the first passivation layer has a storage contact hole exposing the storage electrode.

23. The method according to claim 21, further comprising forming a gate pad at one end of the gate line.

24. The method according to claim 23, further comprising forming a gate pad terminal on the gate pad, a data pad terminal on the data pad and a storage terminal on the storage electrode, wherein the gate pad terminal, the data pad terminal and the storage terminal include a transparent conductive material.

25. The method according to claim 17, wherein the forming the thin film transistor includes:

forming a gate electrode extending from the gate line;

sequentially forming an intrinsic amorphous silicon layer, a doped amorphous silicon layer and a first metal layer on the gate insulating layer; and

etching the first metal layer, the doped amorphous silicon layer and the intrinsic amorphous silicon layer to form a semiconductor layer on the gate insulating layer over the gate electrode, a source electrode on the semiconductor layer and the drain electrode spaced apart from the source electrode.

26. The method according to claim 25, wherein the etching the first metal layer, the doped amorphous silicon layer and the intrinsic amorphous silicon layer comprises:

forming a second photoresist layer on the first metal layer;

exposing and developing the second photoresist layer using a mask having transmissive region, a blocking region and a half-transmissive region such that a transmittance of the half-transmissive region is greater than a transmittance of the blocking region and smaller than a transmittance of the transmissive region to form a second photoresist pattern corresponding to the gate electrode and a third photoresist pattern corresponding to the source electrode, the drain electrode and the data line, the second photoresist pattern being thinner than the third photoresist pattern;

etching the first metal layer, the doped amorphous silicon layer and the intrinsic amorphous silicon layer using the second and third photoresist patterns as an etch mask to form a source-drain pattern and the data line;

removing the second photoresist pattern to expose a portion of the source-drain pattern corresponding to the gate electrode;

etching the first metal layer and the doped amorphous silicon layer using the third photoresist pattern as an etch mask; and

removing the third photoresist pattern.

27. The method according to claim 17, wherein the anisotropically removing the first photoresist layer is performed by an ashing method.

28. A method of fabricating an array substrate for a transflective liquid crystal display device, comprising:

forming a gate line and a data line on a substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;

forming a gate insulating layer between the gate line and the data line;

forming a thin film transistor connected to the gate line and the data line;

forming a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the gate insulating layer on the substrate in the transmissive area;

forming a second passivation layer on the first passivation layer;

forming a first photoresist pattern on the second passivation layer, the first photoresist pattern exposing the drain contact hole and the through hole;

etching the second passivation layer and the gate insulating layer using the first photoresist pattern as an etch mask such that the drain electrode is exposed through the drain contact hole and the substrate is exposed through the through hole;

forming a transparent conductive material layer on the first photoresist pattern and on the second passivation layer;

changing the crystalline state of the transparent conductive material layer such that the crystalline state of first portions of the transparent conductive material layer on the first passivation layer are different than second portions of the transparent conductive material layer over the first passivation layer;

forming a first photoresist layer on the transparent conductive material layer;

anisotropically removing the first photoresist layer to form a second photoresist pattern on the transparent conductive material layer in the drain contact hole and the through hole;

selectively etching the second portions of the transparent conductive material layer to form a drain terminal in the drain contact hole and a pixel electrode in the through hole;

removing the first and second photoresist patterns; and

forming a reflective plate on the drain terminal and the pixel electrode, the reflective plate contacting the drain terminal and the pixel electrode.

29. The method according to claim 28, wherein changing the crystalline state includes one of a laser process or ultraviolet treatment after forming the transparent conductive layer.

30. The method according to claim 28, wherein changing the crystalline state includes a laser or thermal process after forming the second photoresist pattern.

31. An array substrate for a transflective liquid crystal display device, comprising:

a substrate;

a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;

a thin film transistor electrically connected to the gate line and the data line;

a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area;

a pixel electrode contacting the substrate in the transmissive area and a first sidewall of the through hole;

a drain terminal contacting the drain electrode and a second sidewall of the drain contact hole; and

a reflective plate on the first passivation layer, the reflective plate contacting the pixel electrode on the first sidewall of the through hole and covering the drain terminal.

32. The array substrate according to claim 31, wherein the reflective plate exposes the pixel electrode on the substrate in the transmissive area.

33. The array substrate according to claim 31, wherein the pixel electrode is formed of the same layer as the drain terminal.

34. The array substrate according to claim 31, further comprising a storage capacitor electrically connected to the reflective plate, wherein the storage capacitor includes a storage electrode and the first passivation layer has a storage contact hole exposing the storage electrode.

35. The array substrate according to claim 34, further comprising a storage terminal contacting the storage electrode and a sidewall of the storage contact hole, wherein the reflective plate covers the storage electrode.

36. The array substrate according to claim 35, wherein the storage terminal and the drain terminal are formed of the same layer as the pixel electrode.