Method of operating flash memory chips

• US 20070058431A1
• Filed: 12/29/2005
• Published: 03/15/2007
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Yang, Joong, Chung, Jun
• Granted Patent: US 7,502,885 B2
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A method of operating a packaged flash memory module includes applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module; applying a second program or erase command and a second address associated with the second commend to a second flash memory chip of the plurality of flash memory chips that are arranged within the packaged flash memory module, the second command being applied to the second flash memory chip prior to the completion of the first command by the first flash memory chip; and determining whether or not the first flash memory chip has completed the first command. If the first command is determined to have not been completed by the first memory chip, examining whether or not a second flash memory chip has completed the second command. If the first command is determined to have been completed by the first flash memory chip, examining whether or not the completed first command corresponds to a last page of the first flash memory chip.

Claims

1. A method of operating a packaged flash memory device, the method comprising:

sequentially applying a first command to perform an operation and a first address associated with the operation to N flash memory chips that are vertically arranged within the packaged flash memory device; and

thereafter determining whether or not a first flash memory chip has completed the operation;

if the operation is determined to have not been completed by the first memory chip, examining whether or not a second flash memory chip has completed the operation; and

if the operation is determined to have been completed by the first flash memory chip, examining whether or not the operation completed corresponds to a last page of the first flash memory chip.

2. The method of claim 1, further comprising:

if the operation completed corresponds to the last page of the first flash memory chip, examining whether or not the second flash memory chip has completed the operation; and

if the operation completed does not correspond to the last page of the first flash memory chip, applying a second command to perform a second operation and a second address associated with the second operation to the first flash memory chip.

3. The method of claim 2, wherein the first and second operations are operations of the same type.

4. The method of claim 2, wherein the second address is an address obtained by incrementing the first address by a given integer, wherein the flash memory device is a NAND device.

5. The method as claimed in claim 1, further comprising:

determining whether or not the second flash memory chip has completed the operation;

if the operation is determined to have not been completed by the second memory chip, examining whether or not a third flash memory chip has completed the operation; and

if the operation is determined to have been completed by the second flash memory chip, examining whether or not the operation completed corresponds to a last page of the second flash memory chip,

wherein determining steps corresponding to the determining steps with respect to the first and second flash memory chips are sequentially performed until the determining step is performed with respect to the N^th flash memory chip.

6. The method of claim 5, wherein if the operation is determined to have been completed by the in the N^th flash memory chip, examining whether or not the operation completed corresponds to a last page of the N^th flash memory chip, and

wherein if the operation completed corresponds to the last page of the N^th flash memory chip, the operation is stopped with respect to the first to N^th flash memory chips.

7. The method as claimed in claim 1, wherein the second flash memory chip is applied the first command and the first address prior to the completion of the first command by the first flash memory chip.

8. The method as claimed in claim 1, wherein a plurality of the first commands applied to the first to N^th flash memory chips is program command, an erase command or a read command.

9. The method as claimed in claim 1, wherein the first commands applied to the first to N^th flash memory chips are not all the same type of commands.

10. The method as claimed in claim 1, wherein when the first and second commands are different types of commands.

11. The method as claimed in claim 2, wherein the second address is obtained by randomly increasing the first address.

12. The method as claimed in claim 2, wherein the second address is obtained by increasing the first address by one.

19. The method of claim 1, wherein the plurality of flash memory chips are NAND chips that are vertically stacked, the method further comprising:

if the first command completed corresponds to the last page of the first flash memory chip, examining whether or not the second flash memory chip has completed the second command; and

if the operation completed does not correspond to the last page of the first flash memory chip, applying a third program or erase command to and a second address to the first flash memory chip.

13. A method of operating flash memory chips, the method comprising:

(a) sequentially applying an operation command and an address to N flash memory chips stacked vertically;

(b) checking whether or not an operation corresponding to the operation command applied to a first flash memory chip has been completed, as a result of the check, if the operation of the first flash memory chip is determined not to have been completed, checking whether or not an operation corresponding to the operation command applied to a second flash memory chip has been completed, and as a result of the check, if the operation corresponding to the operation applied to the first flash memory chip is determined to have been completed, determining whether or not the operation has been completed corresponds to a last page of the first flash memory chip;

(c) as a result of the determination, if the operation completed by the first flash memory chip is determined to be the last page of the first flash memory chip, checking whether or not the operation corresponding to the operation command applied to the second flash memory chip has been completed, and as a result of the determination, if the operation completed by the first flash memory chip does not correspond to the last page of the first flash memory, applying another operating command and another address to the first flash memory chip, and then checking whether or not the operation has been completed by the second flash memory chip;

(d) if the operation has not been completed after checking an N^th flash memory chip by sequentially performing the steps (b) and (c), allowing the process to return to the step (b), and if the operation has been completed, determining whether or not the operation completed corresponds to a last page of the N^th flash memory chip; and

(e) as a result of the determination, if the operation completed corresponds to the last page of the N^th flash memory chip, returning to the step (b), and if the operation completed does not correspond to the last page of the N^th flash memory chip, applying another operating command and another address to the N^th flash memory chip, and then returning to the step (b).

14. The method as claimed in claim 13, wherein in the step of determining whether the operation completed corresponds to the last page of the N^th flash memory chip, if the operation has been completed with respect to the last pages of all of the N flash memory chips, the operation of the all N flash memory chips is stopped.

15. The method as claimed in claim 13, wherein in the step of sequentially applying the operation command and the address to the N flash memory chips, the operating command and the address are applied to a flash memory chip that will be driven next, before the operation of a flash memory chip that has previously received the operation command is finished.

16. The method as claimed in claim 13, wherein the operating command applied to the first to N^th flash memory chips is program operation command, an erase operating command or a read operating command.

17. The method as claimed in claim 13, wherein when the address is increased and the operating command and the increased address are then applied to the first to N^th flash memory chips, an operating command of a different kind from the operating command that has been previously applied is applied.

18. A method of operating a packaged flash memory module, the method comprising:

applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module;

applying a second program or erase command and a second address associated with the second commend to a second flash memory chip of the plurality of flash memory chips that are arranged within the packaged flash memory module, the second command being applied to the second flash memory chip prior to the completion of the first command by the first flash memory chip; and

determining whether or not the first flash memory chip has completed the first command;

if the first command is determined to have not been completed by the first memory chip, examining whether or not a second flash memory chip has completed the second command; and

if the first command is determined to have been completed by the first flash memory chip, examining whether or not the completed first command corresponds to a last page of the first flash memory chip.

20. The method of claim 18, wherein the plurality of flash memory chips are NAND chips, the method further comprising:

if the first command completed corresponds to the last page of the first flash memory chip, examining whether or not the second flash memory chip has completed the second command; and

if the operation completed does not correspond to the last page of the first flash memory chip, applying a third program or erase command to and a second address to the first flash memory chip,

wherein the plurality of flash memory chips are at least four chips.

21. The method of claim 20, wherein the plurality of flash memory chips are vertically stacked on each other, wherein a third flash memory device is provided between the first and second flash memory chips.