Erase and Program Method of Flash Memory Device for Increasing Program Speed of Flash Memory Device

• US 20070058446A1
• Filed: 12/21/2005
• Published: 03/15/2007
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Hyung, Lee, Min, Hwang, Kyung, Kim, Ju, Kim, Sook, Noh, Keum, Joo, Seok
• Granted Patent: US 7,539,057 B2
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

The present invention relates to erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method according to the present invention, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Claims

1. An erase method of a flash memory device including a plurality of Multi Level Cells (MLCs) that share word lines and bit lines, the erase method comprising the steps of:

pre-programming some of the plurality of MLCs so that a range in which threshold voltages of the plurality of MLCs are distributed is reduced;

erasing the plurality of MLCs; and

verifying whether the plurality of MLCs has been normally erased.

2. The erase method as claimed in claim 1, wherein the pre-programming step includes the steps of:

selecting one of the word lines;

programming some of MLCs connected to the selected word line, of the plurality of MLCs;

determining whether some of the MLCs connected to the selected word line have been programmed;

repeating the selection step, the program step and the determination step until some of the MLCs connected to the selected word line are programmed; and

repeatedly performing the selection step to the repetition step until some of MLCs connected to a last word line, of the plurality of MLCs, are programmed.

3. The erase method as claimed in claim 2, wherein the program step includes the steps of:

selecting MLCs, each having threshold voltages included in any one of first to fourth voltage ranges, of the MLCs connected to the selected word line;

programming the selected MLCs so that the threshold voltages of the selected MLCs are moved to one of the remaining voltage ranges other than a voltage range in which the threshold voltages of the selected MLCs are included, of the first to fourth voltage ranges; and

prohibiting program into the remaining MLCs other than the selected MLCs when the selected MLCs are programmed.

4. The erase method as claimed in claim 3, wherein the highest voltage of the first voltage range is lower than the lowest voltage of the second voltage range, the highest voltage of the second voltage range is lower than the lowest voltage of the third voltage range, and the highest voltage of the third voltage range is lower than the lowest voltage of the fourth voltage range, and

in the step of selecting the MLCs, MLCs respectively having threshold voltages included in the first voltage range, are selected.

5. The erase method as claimed in claim 4, wherein in the step of programming the selected MLCs, when the selected MLCs are programmed, the threshold voltages of the selected MLCs are moved from the first voltage range to the second voltage range.

6. The erase method as claimed in claim 4, wherein in the step of programming the selected MLCs, when the selected MLCs are programmed, the threshold voltages of the selected MLCs are moved from the first voltage range to the fourth voltage range.

7. The erase method as claimed in claim 4, wherein the step of selecting the MLCs includes the steps of:

reading data from the MLCs connected to the selected word line by applying a verify voltage, which is higher than the highest voltage of the first voltage range and is lower than or the same as the lowest voltage of the second voltage range, to the selected word line;

generating verify data based on the read data; and

filtering MLCs whose threshold voltages are included in the first voltage range, of the MLCs connected to the selected word line, according to logic values of the verify data,

wherein in the step of generating the verify data, sensing data generated based on some of the read data are stored in page buffers, respectively, which are connected to the filtered MLCs, as program data through some of the bit lines.

8. The erase method as claimed in claim 2, wherein the program step includes the steps of:

selecting MLCs, each having threshold voltages included in a first voltage range of the first to fourth voltage ranges, of the MLCs connected to the selected word line;

programming the selected MLCs so that the threshold voltages of the selected MLCs are moved to the second voltage range;

prohibiting program into the remaining MLCs other than the selected MLCs when the selected MLCs are programmed;

additionally selecting MLCs respectively having threshold voltages included in the second voltage range, of the plurality of MLCs;

additionally programming the additionally selected MLCs so that the threshold voltages of the additionally selected MLCs are moved to the third voltage range; and

prohibiting program into the remaining MLCs other than the additionally selected MLCs when the additionally selected MLCs are additionally programmed.

9. The erase method as claimed in claim 8, wherein the highest voltage of the first voltage range is lower than the lowest voltage of the second voltage range, the highest voltage of the second voltage range is lower than the lowest voltage of the third voltage range, and the highest voltage of the third voltage range is lower than the lowest voltage of the fourth voltage range.

10. The erase method as claimed in claim 8, wherein the step of selecting the MLCs includes the steps of:

reading data from the MLCs connected to the selected word line by applying a verify voltage, which is higher than the highest voltage of the first voltage range and is lower than or the same as the lowest voltage of the second voltage range, to the selected word line;

generating verify data based on the read data; and

filtering MLCs whose threshold voltages are included in the first voltage range, of the MLCs connected to the selected word line, according to logic values of the verify data,

wherein in the step of generating the verify data, sensing data generated based on some of the read data are stored in page buffers, respectively, which are connected to the filtered MLCs, as program data through some of the bit lines.

11. The erase method as claimed in claim 8, wherein the step of additionally selecting the MLCs includes the steps of:

reading data from the MLCs connected to the selected word line by applying a verify voltage, which is higher than the highest voltage of the second voltage range and is lower than or the same as the lowest voltage of the third voltage range, to the selected word line;

generating verify data based on the read data; and

filtering MLCs whose threshold voltages are included in the second voltage range, of the MLCs connected to the selected word line, according to logic values of the verify data,

wherein in the step of generating the verify data, sensing data generated based on some of the read data are stored in page buffers, respectively, which are connected to the filtered MLCs, as program data through some of the bit lines.

12. The erase method as claimed in claim 8, wherein the verify step includes the steps of:

initializing an upper bit register and a lower bit register of each of page buffers connected to the MLCs, which are connected to the selected word line, through the bit lines;

reading data from the MLCs connected to the selected word line by applying an erase verify voltage to the selected word line;

storing lower sensing data in the lower bit registers of the page buffers based on the read data;

transferring initial data, which are stored in an upper bit register of each of page buffers connected to repaired MLCs of the MLCs connected to the selected word line, to the lower bit registers;

generating verify data based on the lower sensing data or the initial data, which are respectively stored in the lower bit registers of the page buffers; and

determining whether the erase of the MLCs connected to the selected word line is fail depending on logic values of the verify data.

13. The erase method as claimed in claim 1, further comprising the step of post-programming the plurality of MLCs so that threshold voltages of over-erased MLCs, of the plurality of MLCs, are included in a predetermined voltage range, between the erase step and the verify step.

14. The erase method as claimed in claim 13, wherein the pre-program step includes the steps of:

selecting one of the word lines;

programming some of MLCs connected to the selected word line, of the plurality of MLCs;

determining whether some of the MLCs connected to the selected word line have been programmed;

repeating the selection step, the program step and the determination step until some of the MLCs connected to the selected word line are programmed; and

repeatedly performing the selection step to the repetition step until some of MLCs connected to a last word line, of the plurality of MLCs, are programmed.

15. The erase method as claimed in claim 14, wherein the program step includes the steps of:

selecting MLCs respectively having threshold voltages included in the first voltage range of the first to fourth voltage ranges, of the MLCs connected to the selected word line;

programming the selected MLCs so that the threshold voltages of the selected MLCs are moved to the fourth voltage range;

prohibiting program into the remaining MLCs other than the selected MLCs when the selected MLCs are programmed;

additionally selecting MLCs respectively having threshold voltages included in the second voltage range, of the plurality of MLCs;

additionally programming the additionally selected MLCs so that the threshold voltages of the additionally selected MLCs are moved to the third voltage range; and

prohibiting program into the remaining MLCs other than the additionally selected MLCs when the additionally selected MLCs are additionally programmed.

16. The erase method as claimed in claim 15, wherein the highest voltage of the first voltage range is lower than the lowest voltage of the second voltage range, the highest voltage of the second voltage range is lower than the lowest voltage of the third voltage range, and the highest voltage of the third voltage range is lower than the lowest voltage of the fourth voltage range.

17. The erase method as claimed in claim 15, wherein the step of selecting the MLCs includes the steps of:

reading data from the MLCs connected to the selected word line by applying a verify voltage, which is higher than the highest voltage of the first voltage range and is lower than or the same as the lowest voltage of the second voltage range, to the selected word line;

generating verify data based on the read data; and

filtering MLCs whose threshold voltages are included in the first voltage range, of the MLCs connected to the selected word line, according to logic values of the verify data,

wherein in the step of generating the verify data, sensing data generated based on some of the read data are stored in page buffers, respectively, which are connected to the filtered MLCs, as program data through some of the bit lines.

18. The erase method as claimed in claim 15, wherein the step of additionally selecting the MLCs includes the steps of:

reading data from the MLCs connected to the selected word line by applying a verify voltage, which is higher than the highest voltage of the second voltage range and is lower than or the same as the lowest voltage of the third voltage range, to the selected word line;

generating verify data based on the read data; and

filtering MLCs whose threshold voltages are included in the second voltage range, of the MLCs connected to the selected word line, according to logic values of the verify data,

wherein in the step of generating the verify data, sensing data generated based on some of the read data are stored in page buffers, respectively, which are connected to the filtered MLCs, as program data through some of the bit lines.

19. The erase method as claimed in claim 13, wherein the post-program step includes the step of:

selecting one of the word lines;

programming the MLCs connected to the selected word line by applying a program voltage that gradually rises to the selected word line;

initializing an upper bit register and a lower bit register of each of page buffers, which are connected to the MLCs connected to the selected word line through the bit lines;

reading first data from the MLCs connected to the selected word line by applying a first erase verify voltage to the selected word line;

storing first lower sensing data in the lower bit registers of the page buffers, respectively, based on the first data;

transferring initial data, which are respectively stored in upper bit registers of page buffers connected to repaired MLCs of the MLCs connected to the selected word line, to the lower bit registers, respectively;

generating first verify data based on the first lower sensing data or the initial data stored in the lower bit registers, respectively;

determining whether at least one of the threshold voltages of the MLCs connected to the selected word line is higher than the first erase verify voltage according to logic values of the first verify data;

repeating the program step to the determination step until at least one of the threshold voltages of the MLCs connected to the selected word line becomes higher than the first erase verify voltage; and

repeatedly executing the selection step to the repetition step until the selected word line becomes a last word line.

20. The erase method as claimed in claim 19, wherein the verify step includes the steps of:

initializing an upper bit register and a lower bit register of each of the page buffers;

reading second data from the MLCs connected to the selected word line by applying a second erase verify voltage to the selected word line;

storing second lower sensing data in the lower bit registers of the page buffers based on the second data;

transferring the initial data, which are stored in the upper bit registers of the page buffers connected to the repaired MLCs, to the lower bit registers;

generating second verify data based on the second lower sensing data or the initial data, which are respectively stored in the lower bit registers; and

determining whether the erase of the MLCs connected to the selected word line is fail depending on logic values of the second verify data.

21. The erase method as claimed in claim 20, wherein the second erase verify voltage is higher than the first erase verify voltage.

22. The erase method as claimed in claim 20, wherein the first erase verify voltage is 0V.

23. A program method of a flash memory device including a plurality of memory cells that share word lines and bit lines, the program method comprising the steps of:

selecting one of the word lines;

programming memory cells connected to the selected word line, of the plurality of memory cells, by applying a start program voltage to the selected word line;

selecting memory cells respectively having threshold voltages lower than a predetermined voltage, of the memory cells connected to the selected word line;

programming the selected memory cells by applying a pre-program voltage to the selected word line;

prohibiting program into the remaining memory cells other than the selected memory cells when the selected memory cells are programmed; and

additionally programming the memory cells connected to the selected word line, while supplying a program voltage that gradually rises from the start program voltage at the ratio of the step voltage to the selected word line.

24. The program method as claimed in claim 23, wherein the predetermined voltage is 0V.

25. The program method as claimed in claim 23, wherein the pre-program voltage is higher than the start program voltage, and is lower than or the same as a program voltage that has risen by maximum in the additional program step.

26. The program method as claimed in claim 23, wherein the step of selecting the memory cells includes the steps of:

reading first data from the memory cells connected to the selected word line by applying a first verify voltage to the selected word line;

generating first verify data based on the first data; and

filtering memory cells respectively having threshold voltages lower than a predetermined voltage, of the memory cells connected to the selected word line, according to logic values of the first verify data,

wherein in the step of generating the first verify data, sensing data generated based on some of the first data are stored in page buffers of the filterer memory cells, respectively, as program data through some of the bit lines.

27. The program method as claimed in claim 26, wherein the first verify voltage is lower than or the same as the predetermined voltage.

28. The program method as claimed in claim 26, wherein the first verify voltage is a negative voltage.

29. The program method as claimed in claim 26, wherein the memory cells are MLCs.

30. The program method as claimed in claim 29, wherein the additional program step includes the steps of:

first programming the MLCs connected to the selected word line by applying a first program voltage, which gradually rises from the start program voltage at the ratio of the step voltage, to the selected word line;

second programming the MLCs connected to the selected word line by applying a second program voltage gradually rising from the first program voltage, which has finally risen in the first program step, at the ratio of the step voltage to the selected word line; and

third programming the MLCs connected to the selected word line by applying a third program voltage gradually rising from the second program voltage, which has finally risen in the second program step, at the ratio of the step voltage to the selected word line.

31. The program method as claimed in claim 30, wherein the first program step includes:

a first supply step of supplying the first program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading first data from the MLCs connected to the selected word line by applying a second verify voltage to the selected word line;

a step of generating first verify data based on the first data;

a first determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the first verify data; and

a step of repeating the first supply step to the first determination step until the program of the MLCs connected to the selected word line is completed,

wherein the first program voltage, which is applied to the selected word line in the first supply step performed after the first determination step, is a step voltage higher than the first program voltage, which is applied to the selected word line in the first supply step executed prior to the first determination step.

32. The program method as claimed in claim 31, wherein the second verify voltage is higher than the first verify voltage.

33. The program method as claimed in claim 31, wherein the second program step includes:

a second supply step of supplying the second program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading second data from the MLCs connected to the selected word line by applying a third verify voltage to the selected word line;

a step of generating second verify data based on the second data;

a second determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the second verify data; and

a step of repeating the second supply step to the second determination step until the program of the MLCs connected to the selected word line is completed,

wherein the second program voltage, which is applied to the selected word line in the second supply step performed after the second determination step, is the step voltage higher than the second program voltage, which is applied to the selected word line in the second supply step executed prior to the second determination step.

34. The program method as claimed in claim 33, wherein the third verify voltage is higher than the second verify voltage.

35. The program method as claimed in claim 33, wherein the third program step includes:

a third supply step of supplying the third program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading third data from the MLCs connected to the selected word line by applying a fourth verify voltage to the selected word line;

a step of generating third verify data based on the third data;

a third determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the third verify data; and

a step of repeating the third supply step to the third determination step until the program of the MLCs connected to the selected word line is completed,

wherein the third program voltage, which is applied to the selected word line in the third supply step performed after the third determination step, is the step voltage higher than the third program voltage, which is applied to the selected word line in the third supply step executed prior to the third determination step.

36. The program method as claimed in claim 35, wherein the fourth verify voltage is higher than the third verify voltage.

37. The program method as claimed in claim 36, wherein the memory cells are SLCs.

38. The program method as claimed in claim 37, wherein the additional program step includes the steps of:

applying a first program voltage, which has risen as much as the step voltage from the start program voltage, to the selected word line so that the SLCs connected to the selected word line are programmed;

reading data from the SLCs connected to the selected word line by applying a second verify voltage to the selected word line;

generating verify data based on the data;

determining whether the program of the SLCs connected to the selected word line has been completed according to logic values of the verify data; and

repeating the supply step to the determination step until the program of the SLCs connected to the selected word line is completed,

wherein the first program voltage applied to the selected word line in the supply step executed after the determination step is the step voltage higher than the first program voltage applied to the selected word line in the supply step executed prior to the determination step.

39. The program method as claimed in claim 38, wherein the second verify voltage is higher than the first verify voltage.

40. A program method of a flash memory device including a plurality of memory cells that share word lines and bit lines, the program method comprising the steps of:

selecting one of the word lines;

programming memory cells connected to the selected word line by applying a start program voltage that gradually rises at the ratio of a step voltage to the selected word line in each of first to P^th (P is an integer) program cycles;

selecting memory cells respectively having threshold voltages lower than a predetermined voltage, of the memory cells connected to the selected word line;

programming the selected memory cells by applying a pre-program voltage to the selected word line;

prohibiting program into the remaining memory cells other than the selected memory cells when the selected memory cells are programmed; and

additionally programming the memory cells connected to the selected word line, while supplying a program voltage that gradually rises from the start program voltage that has finally rises in the step of programming the memory cells at the ratio of the step voltage to the selected word line.

41. The program method as claimed in claim 40, wherein the P is smaller than or the same as 3.

42. The program method as claimed in claim 40, wherein the pre-program voltage is higher than the start program voltage that has finally risen in the step of programming the memory cells, or lower than or the same as a program voltage that has risen by maximum in the step of additionally programming the memory cells.

43. The program method as claimed in claim 40, wherein the memory cells are MLCs.

44. The program method as claimed in claim 43, wherein the additional program step includes the steps of:

first programming the MLCs connected to the selected word line by applying a program voltage that gradually rises from the start program voltage that has finally risen in the step of programming the memory cells at the ratio of the step voltage to the selected word line;

second programming the MLCs connected to the selected word line by applying a second program voltage that gradually rises from the first program voltage that has finally risen in the first program step at the ratio of the step voltage to the selected word line; and

third programming the MLCs connected to the selected word line by applying a third program voltage that gradually rises from the second program voltage that has finally risen in the second program step at the ratio of the step voltage to the selected word line.

45. The program method as claimed in claim 40, wherein the memory cells are SLCs.

46. The program method as claimed in claim 45, wherein the additional program step includes the steps of:

applying a first program voltage, which has risen as much as the step voltage from the start program voltage that has finally risen in the step of programming the memory cells, to the selected word line so that the SLCs connected to the selected word line are programmed;

reading data from the SLCs connected to the selected word line by applying a second verify voltage to the selected word line;

generating verify data based on the data;

determining whether the program of the SLCs connected to the selected word line has been completed according to logic values of the verify data; and

repeating the supply step to the determination step until the program of the SLCs connected to the selected word line is completed,

wherein the first program voltage applied to the selected word line in the supply step executed after the determination step is the step voltage higher than the first program voltage applied to the selected word line in the supply step executed prior to the determination step.

47. A program method of a flash memory device including a plurality of MLCs that share word lines and bit lines, the program method comprising the steps of:

selecting one of the word lines;

first programming the MLCs connected to the selected word line by applying a first program voltage that gradually rises from a start program voltage at the ratio of a first step voltage to the selected word line; and

first programming the MLCs connected to the selected word line by applying a second program voltage that gradually rises from the first program voltage, which has finally risen in the first program step, at the ratio of a second step voltage.

48. The program method as claimed in claim 47, wherein the second step voltage is higher than the first step voltage.

49. The program method as claimed in claim 47, wherein the first program step includes:

a first supply step of supplying the first program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading first data from the MLCs connected to the selected word line by applying a first verify voltage to the selected word line;

a step of generating first verify data based on the first data;

a first determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the first verify data; and

a step of repeating the first supply step to the first determination step until the program of the MLCs connected to the selected word line is completed,

wherein the first program voltage, which is applied to the selected word line in the first supply step performed after the first determination step, is the first voltage higher than the first program voltage, which is applied to the selected word line in the first supply step executed prior to the first determination step.

50. The program method as claimed in claim 49, wherein the second program step includes:

a second supply step of supplying the second program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading second data from the MLCs connected to the selected word line by applying a second verify voltage to the selected word line;

a step of generating second verify data based on the second data;

a second determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the second verify data; and

a step of repeating the second supply step to the second determination step until the program of the MLCs connected to the selected word line is completed,

wherein the second program voltage, which is applied to the selected word line in the second supply step performed after the second determination step, is the second step voltage higher than the second program voltage, which is applied to the selected word line in the second supply step executed prior to the second determination step.

51. The program method as claimed in claim 50, further comprising the step of third programming the MLCs connected to the selected word line by applying the start program voltage that gradually rises from a start voltage at the ratio of the first step voltage to the selected word line, between the selection step and the first program step,

wherein the third program step includes:

a third supply step of supplying the start program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading third data from the MLCs connected to the selected word line by applying a third verify voltage to the selected word line;

a step of generating third verify data based on the third data;

a third determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the third verify data; and

a step of repeating the third supply step to the third determination step until the program of the MLCs connected to the selected word line is completed,

wherein the start program voltage, which is applied to the selected word line in the third supply step performed after the third determination step, is the first step voltage higher than the start program voltage, which is applied to the selected word line in the third supply step executed prior to the third determination step.

52. The program method as claimed in claim 51, wherein the second verify voltage is higher than the first verify voltage and the first verify voltage is higher than the third verify voltage.