Channel interface for conveying digital data having a lower data rate

• US 20070058675A1
• Filed: 09/09/2005
• Published: 03/15/2007
• Est. Priority Date: 09/09/2005
• Status: Abandoned Application

• Current Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Hendrix, Jon David
• Application Number:
  US11/222,535
• Publication Number:
  US 20070058675A1
• Time in Patent Office: Days
• US Class Current: 370/468
• CPC Class Codes: H04J 3/07 using pulse stuffing for systems with different or fluctuating information rates or bit rates
• CPC Class Codes: H04J 3/22 in which the sources have different rates or codes simultaneous speech and digital data or video transmission H04M11/06; see provisional also H04J3/16

Abstract

Digital data is conveyed over a channel having a frame rate greater than the data rate of the digital data. The digital data is produced at the data rate. From frame to frame, determining whether a digital data sample is available. When the sample of the digital data is available, transmitting, in a current allocated transmission slot of a frame, the sample of the digital data. When the sample of the digital data is not available, transmitting, in the current allocated transmission slot, a predetermined value.

Claims

1. A method for conveying digital data at a data rate over a channel having a frame rate greater than the data rate comprises:

producing the digital data at the data rate;

from frame to frame, determining whether a sample of the digital data is available;

when the sample of the digital data is available, transmitting, in a current allocated transmission slot of a frame, the sample of the digital data; and

when the sample of the digital data is not available, transmitting, in the current allocated transmission slot, a predetermined value.

2. The method of claim 1 wherein the frame comprises one-to-five words, wherein each of the one-to-five words includes 18 bits, wherein 16 of the 18 bits are for data and two of the 18 bits are for control information.

3. The method of claim 1 wherein the digital data comprises a radio data system (RDS) data.

4. The method of claim 1 wherein the channel comprises an asynchronous channel.

5. The method of claim 1 further comprises:

determining that the sample of the digital data is available by;

monitoring buffer storage of the digital data; and

when an end of sample indication is stored, setting a flag.

6. The method of claim 1 further comprises:

determining that the sample of the digital data is available by;

determining a number of bits stored of the digital data;

comparing the number of bits stored with a sample bit size; and

when the number of bits stored compares favorably with the sample bit size, setting a flag to indicate that the sample is available.

7. The method of claim 1, wherein the predetermined value comprises a known invalid word.

8. A handheld audio system comprises:

a radio signal decoder integrated circuit operably coupled to produce radio data system (RDS) data, digital left-channel data, and digital right-channel data; and

a digital audio processing integrated circuit operably coupled to the radio signal decoder integrated circuit via a channel, wherein the digital audio processing integrated circuit produces audio signals for audio playback from at least one of the digital left- and right-channel data and a stored digital audio file,

wherein the radio signal decoder integrated circuit includes;

a processing module, and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

from frame to frame, determine whether a sample of the RDS data is available;

when the sample of the RDS data is available, transmitting, in a current allocated transmission slot of a frame, the sample of the RDS data; and

when the sample of the RDS data is not available, transmitting, in the current allocated transmission slot of the frame, a predetermined value.

9. The handheld audio system of claim 8 wherein the frame comprises one-to-five words, wherein each of the one-to-five words includes 18 bits, wherein 16 of the 18 bits are for data and two of the 18 bits are for control information.

10. The handheld audio system of claim 8 wherein the radio signal decoder integrated circuit comprises:

a digital radio interface that provides parallel-to-serial conversions for at least one of;

a left-channel plus right-channel signal of the digital left- and right-channel data;

a left-channel minus right-channel signal of the digital left- and right-channel data;

a received signal strength indication; and

the RDS data.

11. The handheld audio system of claim 8 wherein the channel comprises an asynchronous serial channel, wherein a frame rate of the channel corresponds to a frame rate of the digital left- and right-channel data.

12. The handheld audio system of claim 8 wherein the digital audio processing integrated circuit further functions to:

demodulate and decode the RDS data to produce RDS application information.

13. The handheld audio system of claim 12 wherein the memory further comprises operational instructions that cause the processing module to determine that the sample of the RDS data is available by:

monitoring a buffer storage of the RDS data; and

when an end of sample indication is stored, setting a flag.

14. The handheld audio system of claim 12 wherein the memory further comprises operational instructions that cause the processing module to determine that the sample of the RDS data is available by:

determining a number of bits stored of the RDS data;

comparing the number of bits stored with a sample bit size; and

when the number of bits stored compares favorably with the sample bit size, setting a flag to indicate that the sample is available.

15. The handheld audio system of claim 8, wherein the predetermined value comprises a known invalid word.

16. A digital radio interface comprises:

a digital data buffer module operably coupled to buffer left-plus-right data, left-minus-right data, and radio data system (RDS) data;

a transmission slot module operably coupled to populate, on a frame by frame basis, time slots of a frame of a plurality of frames with the left-plus-right data, left-minus-right data, and RDS data; and

a bitstream stuffer module operably coupled to produce a serial stream of the plurality of frames, wherein each of the plurality of frames includes an allocated transmission slot for the RDS data, wherein the bitstream stuffer module is further operably coupled to;

when the allocated transmission slot for a current frame of the plurality of frames is to be transmitted, determine whether a RDS data ready signal is set;

when the RDS data ready signal is set, transmit the RDS data in the allocated transmission slot; and

when the RDS data ready signal is not set, transmit known invalid data in the allocated transmission slot.

17. The digital radio interface of claim 16 wherein the frame comprises one-to-five words, wherein each of the one-to-five words includes 18 bits, wherein 16 of the 18 bits are for data and two of the 18 bits are for control information.

18. The digital radio interface of claim 16 wherein the digital data buffer module comprises:

a plurality of buffers operably coupled to buffer the left-plus-right data, left-minus-right data, and RDS data.

19. The digital radio interface of claim 16 wherein the transmission slot module comprises:

a plurality of buffers operably coupled to provide the time slots of the frame; and

a multiplexer operably coupled to separate the left-plus-right data, left-minus-right data, and RDS data and to populate therefrom each of the plurality of buffers based on a time slot control signal.

20. The digital radio interface of claim 19 wherein the multiplexer comprises a programmable multiplexer based on a frame length of the frame.

21. A method of transmitting data having a lower data rate than a transmission rate of a channel comprises:

determining a number of bits stored of the data;

comparing the number of bits stored with a predetermined quantity;

when the number of bits stored compares favorably with the predetermined quantity, transmitting the data in an allocated transmission slot of a frame; and

when the number of bits stored does not compare favorably with the predetermined quantity, transmitting invalid data in the allocated transmission slot of the frame.

22. The method of claim 21 wherein the predetermined quantity comprises a sample bit size.

23. The method of claim 21 wherein the predetermined quantity comprises a 2-bit word.