Quasi non-volatile memory for use in a receiver

• US 20070060093A1
• Filed: 09/15/2005
• Published: 03/15/2007
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Green, Brian, Marques, Augusto, Kerth, Donald
• Granted Patent: US 7,979,048 B2
• Time in Patent Office: Days
• US Class Current: 455/296
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Image rejection factors are calibrated for a receiver circuit (106) during an initialization period. The image rejection factors are stored in a quasi non-volatile memory (124) associated with the receiver circuit (106). The quasi non-volatile memory (124) is powered from a first source (V_DD A) during a first receiver mode and from a second source (V_IO) during a second receiver mode.

Claims

1. A method comprising:

calibrating calibration factors for a receiver circuit during an initialization period;

storing the image rejection factors in a quasi non-volatile memory associated with the receiver circuit; and

powering the quasi non-volatile memory from a first source during a first receiver mode and from a second source during a second receiver mode.

2. The method of claim 1 further comprising:

locking the quasi non-volatile memory to prevent write operations at least during the second receiver mode.

3. The method of claim 2 wherein locking the quasi non-volatile memory further comprises:

preventing write operations during a period while power for the quasi non-volatile memory is switching between the second source and the first source.

4. The method of claim 1 flier comprising:

periodically powering the receiver circuit from the first source to test for signals received from a base station.

5. The method of claim 1 further comprising:

turning off power to the receiver circuit during the second transceiver mode.

6. The method of claim 1 wherein the first source comprises a transceiver supply voltage and wherein the second source comprises a low supply voltage at a lower electrical potential than the transceiver supply voltage.

21. The method of claim 1 wherein the calibrating comprises:

calibrating image rejection factors for the receiver circuit during the initialization period.

7. A receiver circuit comprising:

a first supply voltage with a first electrical potential;

a second supply voltage with a second electrical potential; and

a quasi non-volatile memory adapted to store calibration results for the receiver circuit, the quasi non-volatile memory coupled to the first supply voltage and to the second supply voltage and adapted to derive power from a selected one of the first supply voltage and the second supply voltage responsive to a change of state of at least a portion of the receiver circuit.

8. The receiver circuit of claim 7 wherein the first electrical potential is greater than the second electrical potential.

9. The receiver circuit of claim 7 wherein a first state of the receiver circuit comprises:

an active receive state during which the first supply voltage remains active.

10. The receiver circuit of claim 9 wherein the quasi non-volatile memory derives power from the first supply voltage during the active receive state.

11. The receiver circuit of claim 7 wherein a second state of the receiver circuit comprises:

an inactive state during which the first supply voltage is shut off.

12. The receiver circuit of claim 11 wherein the quasi non-volatile memory derives power from the second supply voltage during the inactive state.

13. The receiver circuit of claim 11 further comprising:

a memory protection unit adapted to prevent writing to the quasi non-volatile memory while the receiver circuit is in an inactive state or in between states.

14. The receiver circuit of claim 7 further comprising:

a power switch for switching power to the quasi non-volatile memory from either the first supply voltage or the second supply voltage responsive to the change of state.

15. A receiver comprising:

a memory;

processing circuitry coupled to the memory, the processing circuitry having an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency, the processing circuitry comprising one or more independently powered components adapted to write data to the memory; and

a memory protection unit coupled to the memory, the memory protection unit adapted to monitor a power supply voltage level corresponding to each of the one or more independently powered components and, if the power supply voltage level changes, to prevent write operations by a corresponding one of the one or more independently powered components at least while the power supply voltage level is changing.

16. The receiver of claim 15 further comprising:

a plurality of voltage regulators, each voltage regulator adapted to be shut down independently, each voltage regulator of the plurality of voltage regulators coupled to a respective one of the one or more independently powered components.

17. The receiver of claim 15 wherein the memory protection unit is adapted to lock the memory to prevent write operations prior to any changes to the power supply voltage level.

18. The receiver of claim 15 wherein the memory derives power from a first supply voltage at a first electrical potential during a first mode of operation and from a second supply voltage at a second electrical potential that is less than the first electrical potential during a second mode of operation, wherein the first supply voltage is collapsed during the second mode of operation.

19. The receiver of claim 18 wherein the memory protection unit is adapted to prevent any write operation to the memory during the second mode of operation.

20. The receiver of claim 15 wherein the memory protection unit is adapted to prevent any write operation to the memory if the power supply voltage level falls below a predetermined threshold level.