Data structures and circuit for multi-channel data transfers using a serial peripheral interface

• US 20070061342A1
• Filed: 09/09/2005
• Published: 03/15/2007
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: QUICKFILTER TECHNOLOGIES, LLC
• Inventors: Magdeburger, Thomas, Headley, Aaron
• Granted Patent: US 7,533,106 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate. In the preferred embodiment, the control registers include fields for device identification, a flag for the run or configure mode, a I/O-mode control, a value for the channels active (in multi-channel implementations), the data source clock rate, the ADC clock rate, channel-status flags, the CIC decimation rate, the number of taps for FIR filters, and the filter coefficients corresponding to the number of FIR taps in a particular data source.

Claims

1. a serial interface controller for transferring data between a data source having a:

least one channel and a processor;

the serial interface controller having a plurality of control registers;

the control registers comprising;

a data structure for configuring the serial interface controller for a data transfer;

the data structure further comprising;

a field for selectively setting the serial interface controller in its run mode or its configuration mode;

a field for storing the I/O mode of the serial interface controller;

a field for storing the address of the active data channel; and

,

a field for storing the clock rate of the data source.

2. The serial interface controller of claim 1, where the data source is a CIC digital filter, and the data structure further comprises:

a field for storing the decimation value of the CIC.

3. The serial interface controller of claim 1, where the data source is an FIR digital filter, and the data structure further comprises:

a field for storing the number of filter taps; and

,

a field for storing the coefficients for the FIR filter.

4. The serial interface controller of claim 3, comprising more than one data channel, where the data structure further comprises, for each channel:

a field for storing the number of filter taps for the channel; and

,

a field for storing the coefficients for the FIR filter for that channel.

5. The serial interface controller of claim 1, where the data structure further comprises a field for storing the ADC clock rate for a digital filter.

6. The serial interface controller of claim 1, where the I/O mode field further comprises:

a field for storing the address of the fastest active channel;

a field for selectively storing the serial interface RDY flag for each channel or the fastest channel; and

,

a field for storing a flag for selectively setting either single-channel data transfers or multiple-channel data transfers.

7. The serial interface controller of claim 1, further comprising a means for selectively individually addressing the control registers.

8. The serial interface controller of claim 7, where the means for selectively individually addressing the control registers comprises a configure-mode data structure;

the configure-mode data structure comprising;

a field for selectively setting the data transfer to the addressed control register to read or write;

a field storing an address of the addressed control register; and

,

a field storing data to be written to or read from to the addressed control register.

9. The serial interface controller of claim 8, where the configure-mode data structure is configured so that:

the field for selectively setting the data transfer to the addressed control register to read or write holds one bit;

the field storing an address of the addressed control register holds 14 bits;

the field storing data to be written to or read from the addressed control register holds eight bits; and

,

the configure-mode data structure further comprises a one-bit unused field between the address field and the data field.

10. The serial interface controller of claim 1 further comprising a data structure defining an input and output format for a single-channel run mode;

the data structure so defining an input and output format for a single-channel run mode comprising;

an eight-bit control address field and an eight-bit control-register data field; and

,

a 16-bit data-out field.

11. The serial interface controller of claim 1 further comprising a data structure defining an input and output format for a multiple-channel run mode;

the data structure so defining an input and output format for a multiple-channel run mode comprising;

an eight-bit control-address field;

an eight-bit control-register data field; and

,

an unused eight-bit field.

12. The serial interface of claim 11 further comprising a 24-bit data structure for output data.

13. The serial interface controller of claim 11 where the 24-bit data structure for output data further comprises:

a one-bit parity field;

a two-bit channel-identification field;

a one-bit new-data flag field;

a four-bit status field; and

,

a 16-bit data field.

14. An integrated circuit comprising:

a data source having at least one channel; and

,

a serial interface controller for transferring data between the data source and a processor;

the serial interface controller having a plurality of control registers;

the control registers comprising;

a data structure for configuring the serial interface controller for a data transfer;

the data structure further comprising;

a field for selectively setting the serial interface controller in its run mode or its configuration mode;

a field for storing the I/O mode of the serial interface controller;

a field for storing the address of the active data channel; and

,

a field for storing the system clock rate.

15. The integrated circuit of claim 14, where the data source is a CIC digital filter, and the data structure further comprises:

a field for storing the decimation value of the CIC.

16. The integrated circuit of claim 14, where the data source is an FIR digital filter, and the data structure further comprises:

a field for storing the number of filter taps; and

,

a field for storing the coefficients for the FIR filter.

17. The integrated circuit of claim 16, comprising more than one data channel, where the data structure further comprises, for each channel:

a field for storing the number of filter taps; and

,

a field for storing the coefficients for the FIR filter.

18. The integrated circuit of claim 14, where the data structure further comprises a field for storing the ADC clock rate for a digital filter.

19. The integrated circuit of claim 14, where the I/O mode field further comprises:

a field for storing the address of the fastest active channel;

a field for selectively storing the serial interface RDY flag for each channel or the fastest channel; and

,

a field for storing a flag for selectively setting either single-channel data transfers or multiple-channel data transfers.

20. The integrated circuit of claim 14, further comprising a means for selectively individually addressing the control registers.

21. The integrated circuit of claim 20, where the means for selectively individually addressing the control registers comprises a configure-mode data structure;

the configure-mode data structure comprising;

a field for selectively setting the data transfer to the addressed control register to read or write;

a field storing an address of the addressed control register; and

,

a field storing data to be written to or read from to the addressed control register.

22. The integrated circuit of claim 21, where the configure-mode data structure is configured so that:

the field for selectively setting the data transfer to the addressed control register to read or write holds one bit;

the field storing an address of the addressed control register holds 14 bits;

the field storing data to be written to or read from the addressed control register holds eight bits; and

,

the configure-mode data structure further comprises a one-bit unused field between the address field and the data field.

23. The integrated circuit of claim 14 further comprising a data structure defining an input and output format for a single-channel run mode;

the data structure so defining an input and output format for a single-channel run mode comprising;

an eight-bit control address field and an eight-bit control-register data field; and

,

a 16-bit data-out field.

24. The integrated circuit of claim 14 further comprising a data structure defining an input and output format for a multiple-channel run mode;

the data structure so defining an input and output format for a multiple-channel run mode comprising;

an eight-bit control-address field;

an eight-bit control-register data field; and

,

an unused eight-bit field.

25. The integrated circuit of claim 24 further comprising a 24-bit data structure for output data.

26. The integrated circuit of claim 24 where the 24-bit data structure for output data further comprises:

a one-bit parity-bit field;

a two-bit channel-identification field;

a one-bit new-data flag field;

a four-bit status field; and

,

a 16-bit data field.

27. The integrated circuit of claim 26 where the data structure for output data is clocked out of the serial interface controller to the processor according to the processor clock.

28. The integrated circuit of claim 19, further comprising interface control logic responsive to the flag for selectively setting either single-channel data transfers or multiple-channel data transfers.