Data processing system

• US 20070061463A1
• Filed: 11/08/2005
• Published: 03/15/2007
• Est. Priority Date: 08/25/2005
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hiramatsu, Shinichi, Takeuchi, Hisaharu, Kurokawa, Isamu, Yasuda, Miyuki, Muto, Jyunichi
• Granted Patent: US 7,373,465 B2
• Time in Patent Office: Days
• US Class Current: 709/226
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it possible to expand the number of logical device addresses in excess of the device address limitations of the channel interface, and also enhances the performance of parallel access processing for the same logical device. When an access request is generated for a logical device, the host processing apparatus stores the logical device address to be accessed in a prefix command of a channel command word (CCW) for the access request, sets this CCW in a device information block of a frame which complies with the channel interface, sets a parallel access identifier for identifying a plurality of accesses for the same device in a device address of this frame, and then sends this frame to the storage subsystem.

Claims

1. A data processing system, which comprises a host processing apparatus, and a storage subsystem which is communicatively connected to said host processing apparatus and which has a plurality of logical devices for storing data, wherein:

said host processing apparatus has a channel unit for notifying access requests for the respective logical devices to said storage subsystem,

said storage subsystem has a control processor which controls access processing for the respective logical devices requested by said access request, in response to said access request notified from said host processing apparatus,

when an access request is generated for a certain logical device, said channel unit of said host processing apparatus creates one or more channel command words corresponding to said access request, sets logical device identifying information for identifying said certain logical device in a first field in at least one of said channel command words, creates one or more frames of a prescribed structure, sets said channel command word in a second field within said frame, and then sends said frame to said storage subsystem, and

said control processor of said storage subsystem receives said frame sent from said host processing apparatus, receives said channel command word from said second field of said received frame, acquires said logical device identifying information from said first field of at least one of said received channel command words, specifies which logical device is to be accessed based on said acquired logical device identifying information, and then controls access processing for said access-targeted logical device in accordance with said received channel command word.

2. The data processing system according to claim 1, wherein:

when a plurality of access requests is generated for said certain logical device, said channel unit of said host processing apparatus allocates different parallel access identifying information to each of said plurality of access requests, and then sets said different parallel access identifying information allocated to each of said plurality of access requests, in a third field of said frame for each access request and sends said frame to said storage subsystem, and

said control processor of said storage subsystem acquires said parallel access identifying information from said third field of said received frame, and identifies each of said plurality of access requests for the same logical device in accordance with said acquired parallel access identifying information.

3. The data processing system according to claim 2, wherein:

the size of said first field in said channel command word is larger than the size of said third field in said frame.

4. The data processing system according to claim 2, wherein:

said control processor of said storage subsystem creates a response frame of a prescribed structure for responding to said access request from said host processing apparatus, sets parallel access identifying information allocated to each of said access requests, and logical device identifying information of said access-targeted logical device in said response frame, and then returns said response frame to said host processing apparatus.

5. The data processing system according to claim 2, wherein:

said host processing apparatus further comprises a number of control blocks capable of being allocated to processing operations of different access requests, and

when a plurality of access requests is generated for said certain logical device, said channel unit of said host processing apparatus allocates different control blocks to said plurality of access requests, and then parallelly controls the processing operations of said plurality of access requests using said different control blocks and said different parallel access identifying information allocated to each of said plurality of access requests.

6. The data processing system according to claim 2, wherein:

said channel unit of said host processing apparatus has a plurality of subchannels for respectively storing control information, each of which is used to create said frame for each of the respective access requests, and identifies, from among said plurality of subchannels, a free subchannel which is currently not being used, and when each access request is generated, dynamically allocates the respective free subchannels to said respective access requests.

7. The data processing system according to claim 2, wherein:

said storage subsystem generates, on the basis of a combination of said logical device identifying information acquired from said received channel command word and said parallel access identifying information acquired from said received frame, a plurality of access control blocks respectively allocated to a plurality of access processes for the same logical device, and parallelly controls said plurality of access processes using said plurality of access control blocks.

8. A host processing apparatus in the data processing system, wherein said host processing apparatus has a channel unit for notifying access requests for the respective logical devices to said storage subsystem.

9. A storage subsystem in the data processing system, wherein said storage subsystem has a control processor which controls access processing for the respective logical devices requested by said access request, in response to said access request notified from said host processing apparatus.