Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof

• US 20070063251A1
• Filed: 09/22/2005
• Published: 03/22/2007
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tu, Kuo-Chi, Lee, Hsiang-Fan
• Granted Patent: US 7,355,240 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed therein. Gate electrode and capacitor plate layer components within each of the devices may be formed simultaneously incident to patterning of a single blanket gate electrode material layer

Claims

1. A semiconductor product comprising:

a semiconductor substrate comprising;

a logic region having a logic device formed therein;

a non-volatile memory region having a non-volatile memory device formed therein; and

a 1T-RAM region having a 1T-RAM device formed therein.

2. The product of claim 1 wherein the logic device is a field effect transistor device.

3. The product of claim 1 wherein the non-volatile memory device is an electrically programmable memory device.

4. A 1T-RAM comprising:

a logic region, a non-volatile memory region and a 1T-RAM region, wherein the 1T-RAM region comprises;

a trench in a semiconductor substrate, the trench having at its bottom a shallow trench isolation region;

a junction in a sidewall of the trench;

a dielectric layer overlying the sidewall; and

an upper capacitor electrode on top of the dielectric layer.

5. The 1T-RAM of claim 4 wherein a gate electrode within the logic region, a control gate within the non-volatile memory region and the upper capacitor electrode within the 1T-RAM region are defined at the same time employing a single mask.

6. The 1T-RAM of claim 4 wherein an integrate electrode dielectric layer within the non-volatile memory region and a capacitor dielectric layer within the 1T-RAM region are defined at the same time employing a single mask.

7. The 1T-RAM of claim 4 wherein a gate electrode dielectric layer within the 1T-RAM region and a gate electrode dielectric layer within the logic region are defined at the same time employing a single mask.

8. The 1T-RAM of claim 4 further comprising a single capacitor that comprises a sidewall of an active region of the semiconductor substrate as a capacitor node layer.

9. A method for forming a semiconductor product comprising:

providing a semiconductor substrate; and

defining within the semiconductor substrate;

a logic region and forming a logic device therein;

a non-volatile memory region and forming a non-volatile memory device therein; and

a 1T-RAM region and forming a 1T-RAM device therein.

10. The method of claim 9 wherein the step of providing the semiconductor substrate comprises providing the semiconductor substrate formed from a semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium alloy and semiconductor-on-insulator semiconductor materials.

11. The method of claim 9 wherein the step of forming the logic device comprises forming a field effect transistor device.

12. The method of claim 9 wherein the step of forming the non-volatile memory device comprises forming an electrically programmable memory device.

13. The method of claim 9 wherein the step of forming the 1T-RAM device comprises forming a single transistor and a single capacitor 1T-RAM device.

14. The method of claim 9 wherein the steps of forming the logic device, the non-volatile memory device and the 1T-RAM device comprise forming a gate electrode component of each of the logic device, the non-volatile memory device and the 1T-RAM device simultaneously incident to patterning of a blanket gate electrode material layer.

15. The method of claim 14 wherein within the step of forming the 1T-RAM device comprises forming a capacitor plate layer simultaneously incident to pattering of the blanket gate electrode material layer.

16. The method of claim 13 wherein the step of forming the single capacitor within the single transistor and single capacitor 1T-RAM device comprises forming a single capacitor while employing a sidewall of an active region of the silicon semiconductor substrate as a capacitor node layer.