Floating-gate memory cell

• US 20070063259A1
• Filed: 11/16/2006
• Published: 03/22/2007
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Nirmal, Derderian, Garo
• Granted Patent: US 7,898,017 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a control gate layer overlies the intergate dielectric layer. A first silicon oxide layer is formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extends across a first portion of an edge of the tunnel dielectric layer. A second silicon oxide layer is formed on a sidewall of the trench and extends across a second portion of the edge of the tunnel dielectric layer.

Claims

1. A floating-gate memory cell, comprising:

a tunnel dielectric layer overlying a silicon-containing semiconductor substrate and adjacent a trench formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer comprises at least one silicon-containing layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

a first silicon oxide layer formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extending across a first portion of an edge of the tunnel dielectric layer; and

a second silicon oxide layer formed on a sidewall of the trench and extending across a second portion of the edge of the tunnel dielectric layer.

2. The floating-gate memory cell of claim 1, wherein the tunnel dielectric layer comprises a silicon oxide layer.

3. The floating-gate memory cell of claim 1, wherein the at least one silicon-containing layer is a first polysilicon layer formed overlying and adjoining the tunnel dielectric layer.

4. The floating-gate memory cell of claim 3, wherein the floating-gate layer further comprises a second polysilicon layer overlying and adjoining the first polysilicon layer.

5. A floating-gate memory cell, comprising:

a tunnel oxide layer overlying a silicon-containing semiconductor substrate and positioned between two isolation trenches formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel oxide layer, wherein the floating-gate layer comprises at least one polysilicon layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

first silicon oxide layers formed on opposing edges of the at least one polysilicon layer of the floating-gate layer and extending across a first portion of opposing edges of the tunnel oxide layer; and

second silicon oxide layers formed on sidewalls of the trenches and extending across a second portion of the opposing edges of the tunnel oxide layer.

6. A memory device, comprising:

an array of floating-gate memory cells; and

circuitry for control and/or access of the array of floating-gate memory cells;

wherein the at least one memory cell of the array of floating-gate memory cells comprises;

a tunnel dielectric layer overlying a silicon-containing semiconductor substrate and adjacent a trench formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer comprises at least one silicon-containing layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

a first silicon oxide layer formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extending across a first portion of an edge of the tunnel dielectric layer; and

a second silicon oxide layer formed on a sidewall of the trench and extending across a second portion of the edge of the tunnel dielectric layer.

7. The memory device of claim 6, wherein the array of floating-gate memory cells are arranged and configured as an array type selected from the group consisting of a NAND array of floating-gate memory cells and a NOR array of floating-gate memory cells.

8. The memory device of claim 6, wherein the tunnel dielectric layer comprises a silicon oxide layer.

9. The memory device of claim 6, wherein the at least one silicon-containing layer is a first polysilicon layer formed overlying and adjoining the tunnel dielectric layer.

10. The memory device of claim 9, wherein the floating-gate layer further comprises a second polysilicon layer overlying and adjoining the first polysilicon layer.

11. A memory device, comprising:

an array of floating-gate memory cells; and

circuitry for control and/or access of the array of floating-gate memory cells;

wherein the at least one memory cell of the array of floating-gate memory cells comprises;

a tunnel oxide layer overlying a silicon-containing semiconductor substrate and positioned between two isolation trenches formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel oxide layer, wherein the floating-gate layer comprises at least one polysilicon layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

first silicon oxide layers formed on opposing edges of the at least one polysilicon layer of the floating-gate layer and extending across a first portion of opposing edges of the tunnel oxide layer; and

second silicon oxide layers formed on sidewalls of the trenches and extending across a second portion of the opposing edges of the tunnel oxide layer.

12. The memory device of claim 11, wherein the array of floating-gate memory cells are arranged and configured as an array type selected from the group consisting of a NAND array of floating-gate memory cells and a NOR array of floating-gate memory cells.

13. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

an array of floating-gate memory cells, at least one memory cell comprising;

a tunnel dielectric layer overlying a silicon-containing semiconductor substrate and adjacent a trench formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer comprises at least one silicon-containing layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

a first silicon oxide layer formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extending across a first portion of an edge of the tunnel dielectric layer; and

a second silicon oxide layer formed on a sidewall of the trench and extending across a second portion of the edge of the tunnel dielectric layer; and

circuitry for control and/or access of the array of floating-gate memory cells.

14. The electronic system of claim 13, wherein the array of floating-gate memory cells are arranged and configured as an array type selected from the group consisting of a NAND array of floating-gate memory cells and a NOR array of floating-gate memory cells.

15. The electronic system of claim 13, wherein the tunnel dielectric layer comprises a silicon oxide layer.

16. The electronic system of claim 13, wherein the at least one silicon-containing layer is a first polysilicon layer formed overlying and adjoining the tunnel dielectric layer.

17. The electronic system of claim 16, wherein the floating-gate layer further comprises a second polysilicon layer overlying and adjoining the first polysilicon layer.

18. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

an array of floating-gate memory cells, at least one memory cell comprising;

a tunnel oxide layer overlying a silicon-containing semiconductor substrate and positioned between two isolation trenches formed in the semiconductor substrate;

a floating-gate layer overlying the tunnel oxide layer, wherein the floating-gate layer comprises at least one polysilicon layer;

an intergate dielectric layer overlying the floating-gate layer;

a control gate layer overlying the intergate dielectric layer;

first silicon oxide layers formed on opposing edges of the at least one polysilicon layer of the floating-gate layer and extending across a first portion of opposing edges of the tunnel oxide layer; and

second silicon oxide layers formed on sidewalls of the trenches and extending across a second portion of the opposing edges of the tunnel oxide layer; and

circuitry for control and/or access of the array of floating-gate memory cells.

19. The electronic system of claim 18, wherein the array of floating-gate memory cells are arranged and configured as an array type selected from the group consisting of a NAND array of floating-gate memory cells and a NOR array of floating-gate memory cells.