Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device

• US 20070063317A1
• Filed: 06/22/2006
• Published: 03/22/2007
• Est. Priority Date: 06/24/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Chun-Suk, Kim, Dae-Joung, You, Ji-Yong, Yoo, Do-Yul, Lee, Dae-Youp
• Application Number:
  US11/472,376
• Publication Number:
  US 20070063317A1
• Time in Patent Office: Days
• US Class Current: 257/622
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon substrate, forming a metal silicide layer to be in direct contact with the silicon substrate, and forming a lower overlay mark on the metal silicide layer.

Claims

1. An overlay key formed in a scribe lane region and used to align a circuit pattern comprising a lower overlay mark formed on a first metal silicide layer directly in contact with a silicon substrate.

2. The overlay key of claim 1, further including an upper overlay mark formed above the lower overlay mark.

3. The overlay key of claim 1, wherein the first metal silicide layer includes at least one layer selected from the group consisting of a cobalt silicide layer, a tungsten silicide layer, a titanium silicide layer, and a tantalum silicide layer.

4. The overlay key of claim 1, wherein the first metal silicide layer has a light reflexibility of about 8% to about 30%.

5. A semiconductor device comprising:

a semiconductor structure formed on a chip region, the semiconductor structure including a transistor having a second metal silicide layer, an insulation interlayer, and an upper wiring; and

the overlay key of claim 1.

6. The semiconductor device of claim 5, wherein a material of the first and second metal silicide layers is the same.

7. The semiconductor device of claim 5, wherein the first metal silicide layer includes a layer selected from a group consisting of a cobalt silicide layer, a tungsten silicide layer, a titanium silicide layer, and a tantalum silicide layer.

8. The semiconductor device of claim 7, wherein the first metal silicide layer has a light reflexibility of about 8% to about 30%.

9. The semiconductor device of claim 7, further including an upper overlay mark formed on the lower overlay mark.

10. A method of forming an overlay key in a scribe lane region, comprising:

providing a silicon substrate;

forming a first metal silicide layer in direct contact with the silicon substrate; and

forming a lower overlay mark on the first metal silicide layer.

11. The method of claim 10, further including forming an upper overlay mark on the lower overlay mark.

12. The method of claim 10, wherein forming the first metal silicide layer includes:

forming a metal layer on the silicon substrate; and

thermally treating the silicon substrate and the metal layer to chemically react silicon in the silicon substrate with metal in the metal layer.

13. The method of claim 12, wherein the metal layer includes at least one layer consisting of a cobalt layer, a tungsten layer, a titanium layer, and a tantalum layer.

14. The method of claim 12, wherein the metal layer has a light absorption constant of about 1.5% to about 4%.

15. A method of manufacturing a semiconductor device, comprising:

forming a transistor having a second metal silicide layer on the silicon substrate in a chip region;

forming an overlay key according to claim 10;

forming an insulation interlayer on the transistor;

partially etching the insulation interlayer in the scribe lane region to form the lower overlay mark, wherein the lower overlay mark is trench-shaped;

forming a conductive layer on the chip region and the scribe lane region;

forming a photoresist pattern on the conductive layer in the chip region, and an upper overlay mark on the silicon substrate in the scribe lane region; and

partially etching the conductive layer using the photoresist pattern as an etching mask to form an upper wiring.

16. The method of claim 15, wherein forming the transistor and the first metal silicide layer comprises:

sequentially forming a gate insulation layer and a polysilicon layer pattern on the silicon substrate;

forming a silicidation-blocking layer pattern on the polysilicon layer pattern and the silicon substrate, the silicidation-blocking layer pattern partially exposing surfaces of the polysilicon layer pattern and the silicon substrate in the chip region and wholly exposing the silicon substrate in the scribe lane region;

forming a metal layer on the polysilicon layer pattern, the silicon substrate and the silicidation-blocking layer pattern; and

reacting the metal layer, the silicon substrate, and the polysilicon layer pattern.

17. The method of claim 16, wherein the metal layer includes at least one layer selected from the group consisting of a cobalt layer, a tungsten layer, a titanium layer, and a tantalum layer.

18. The method of claim 16, wherein the metal layer has a light absorption constant of about 1.5% to about 4%.

19. The method of claim 15, further including forming a contact hole in the chip region, the contact hole being formed simultaneously with the lower overlay mark.

20. The method of claim 19, further including depositing a conductive material on inner surfaces of the trench-shaped lower overlay mark and the contact hole.

21. The method of claim 15, wherein the conductive layer includes at least one layer selected from a group consisting of a metal layer and a metal nitride layer.

22. The method of claim 15, further including forming an upper overlay mark on the lower overlay mark.