Circuit and method for bias voltage generation

• US 20070063687A1
• Filed: 09/20/2005
• Published: 03/22/2007
• Est. Priority Date: 09/20/2005
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Yetter, Jeffry, Zhou, Dacheng, Berkram, Daniel
• Granted Patent: US 7,816,975 B2
• Time in Patent Office: Days
• US Class Current: 323/315
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A bias voltage generation circuit is provided which includes a voltage-to-current translation circuit configured to generate a first current that is positively related to a first voltage. A current mirror circuit is configured to generate a first bias voltage that is negatively related to the first current. The current mirror circuit also generates a second current that is positively related to the first current. Also employed is a current-to-voltage translation circuit configured to generate a second bias voltage that is positively related to the second current.

Claims

1. A bias voltage generation circuit, comprising:

a voltage-to-current translation circuit configured to generate a first current that is positively related to a first voltage;

a current mirror circuit configured to generate a first bias voltage that is negatively related to the first current, and configured to generate a second current that is positively related to the first current; and

a current-to-voltage translation circuit configured to generate a second bias voltage that is positively related to the second current.

2. The bias voltage generation circuit of claim 1, further comprising a resistive load circuit configured to provide a resistance coupled with an output, wherein the resistance is positively related to the first bias voltage.

3. The bias voltage generation circuit of claim 2, wherein the output is an output clock signal of a phase interpolator.

4. The bias voltage generation circuit of claim 3, wherein the current mirror circuit and the current-to-voltage translation circuit are physically located closer to the phase interpolator than is the voltage-to-current translation circuit.

5. The bias voltage generation circuit of claim 1, wherein a magnitude of the second current is substantially equal to a magnitude of the first current.

6. The bias voltage generation circuit of claim 1, wherein a magnitude of the second bias voltage is substantially equal to a magnitude of the first voltage.

7. The bias voltage generation circuit of claim 1, wherein the second bias voltage controls a current weighting circuit of a phase interpolator.

8. The bias voltage generation circuit of claim 1, wherein the first voltage is a bias control signal of a voltage-controlled oscillator.

9. The bias voltage generation circuit of claim 1, the voltage-to-current translation circuit comprising:

an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a gate coupled with the first voltage, a drain coupled with the current mirror circuit, and a source coupled with a voltage reference.

10. The bias voltage generation circuit of claim 1, the current mirror circuit comprising:

a first p-channel MOSFET comprising a gate and a drain coupled with the voltage-to-current translation circuit, and a source coupled with a drain voltage; and

a second p-channel MOSFET comprising a gate coupled with the gate of the first p-channel MOSFET, and a source coupled with the drain voltage;

wherein the drain of the first p-channel MOSFET produces the first bias voltage.

11. The bias voltage generation circuit of claim 1, the current-to-voltage translation circuit comprising:

an n-channel MOSFET comprising a gate and a drain coupled with the current mirror circuit, and a source coupled with a voltage reference;

wherein the gate and the drain produce the second bias voltage.

12. The bias voltage generation circuit of claim 2, the resistive load circuit comprising:

a first p-channel MOSFET comprising a gate and a drain coupled with the output, and a source coupled with a drain voltage; and

a second p-channel MOSFET comprising a gate driven by the first bias voltage, a drain coupled with the drain of the first p-channel MOSFET, and a source coupled with the drain voltage.

13. A phase interpolator comprising the bias voltage generation circuit of claim 1.

14. A phase generator comprising the phase interpolator of claim 13.

15. A method of generating a first and second bias voltages, comprising:

providing a first current that is positively related to a first voltage;

generating the first bias voltage, the first bias voltage being negatively related to the first current;

mirroring the first current to yield a second current; and

producing the second bias voltage, the second bias voltage being positively related to the second current.

16. The method of claim 15, further comprising providing a resistance which is positively related to the first bias voltage.

17. The method of claim 16, wherein the resistance is coupled to an output clock signal of a phase interpolator.

18. The method of claim 15, wherein a magnitude of the second current is substantially equal to a magnitude of the first current.

19. The method of claim 15, wherein a magnitude of the second bias voltage is substantially equal to a magnitude of the first voltage.

20. The method of claim 15, wherein the first voltage is a bias control signal of a voltage-controlled oscillator.

21. A phase interpolator employing the method of claim 15.

22. A phase generator comprising the phase interpolator of claim 21.

23. A bias voltage generation circuit, comprising:

means for providing a first current positively related to a first voltage;

means for creating a second current positively related to the first current, the creating means also yielding a first bias voltage which is negatively related to the first current; and

means for producing a second bias voltage which is positively related to the second current.

24. The bias voltage generation circuit of claim 23, further comprising a resistance which is positively related to the first bias voltage.

25. The bias voltage generation circuit of claim 24, wherein the resistance is coupled to an output clock signal of a phase interpolator.

26. The bias voltage generation circuit of claim 23, wherein a magnitude of the second current is substantially equal to a magnitude of the first current.

27. The bias voltage generation circuit of claim 23, wherein a magnitude of the second bias voltage is substantially equal to a magnitude of the first voltage.

28. The bias voltage generation circuit of claim 23, wherein the first voltage is a bias control signal of a voltage-controlled oscillator.

29. A phase interpolator comprising the bias voltage generation circuit of claim 23.

30. A phase generator comprising the phase interpolator of claim 29.