Object shape determination method and system therefor

• US 20070063707A1
• Filed: 05/21/2004
• Published: 03/22/2007
• Est. Priority Date: 05/31/2003
• Status: Active Grant

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Berkel, Cornelis
• Granted Patent: US 7,330,035 B2
• Time in Patent Office: Days
• US Class Current: 324/457
• CPC Class Codes: G06F 3/044 by capacitive means

Abstract

A system employing processing means (12) and electrostatic sensing apparatus (20) is described, the system operating methods in which an unknown object shape is computed from repeated iteration (56) of electrostatic calculations (44,46) on a predetermined shaped object (42,70) and sensed electrostatic measurements (40). The predetermined object shape (70) is morphed towards the unknown object shape (72) at each iteration of the method, until the object shape is determined (60,74). The morphing of the shape is based on calculating the zero contour of the electrostatic potential which depends on a charge distribution applied to the predetermined shape.

Claims

1. A semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, the termination structure comprising a plurality of lateral trenchgate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body, each lateral device comprising a trench having a gate electrode therein separated from the semiconductor body by a layer of gate insulating material, the trenches, gate electrodes and layers of gate insulating material of the lateral devices being formed in the same respective process steps as trenches, insulated electrodes therein and layers of material insulating the insulated electrodes of devices in the active area, the gate electrodes of the lateral devices extending through a region of a first conductivity type, and part way through an underlying region of a second, opposite conductivity type, with each lateral device including an electrically conductive connection between its gate electrode and the first conductivity type region at the side of the lateral device closer to the active area, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices.

2. A semiconductor device of claim 1 wherein the active area comprises devices having a region the first conductivity type which is formed in the same process step as the first conductivity type region of the lateral devices.

3. A semiconductor device of claim 1 or claim 1 wherein the insulated electrodes of the active area devices are gate electrodes of trench-gate transistor devices, and the first conductivity type region of the active area devices forms a channel-accommodating region thereof.

4. A semiconductor device of claim 1 or claim 1 wherein the

insulated electrodes of the active area devices are trenched electrodes of Schottky rectifiers.

5. A semiconductor device of claim 1 wherein the layer of insulating material is thicker over the bottom of the trenches of the lateral devices than over at least a portion of the sidewalls of said trenches.

6. A semiconductor device of preceding claim 1 wherein the doping level of a respective portion of the region of second conductivity type adjacent the bottom of each of the gate trenches of the lateral devices is higher than that of the remainder of the second conductivity type region.

7. A semiconductor device of preceding claim 1 wherein the semiconductor body is rectangular in the plane of the body, and the connections are provided towards one or more comers of the body.

8. A method of forming a semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, the termination structure comprising a plurality of lateral trench-gate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body, each lateral device comprising a trench having a gate electrode therein separated from the semiconductor body by a layer of gate insulating materials, the gate electrodes of the lateral devices extending through a region of a first conductivity type, and part way through an underlying region of a second, opposite conductivity type, with each lateral device including an electrically conductive connection between its gate electrode and the first conductivity type region at the side of the lateral device closer to the active area, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices, the method comprising forming the trenches, gate electrodes and layers of gate insulating material of the lateral devices in the same respective process steps as trenches, insulated electrodes therein and layers of material insulating the insulated electrodes of devices in the active areas.

9. A method of claim 8 comprising forming a region of the first conductivity type in devices of the active area in the same process step as the first conductivity type region of the lateral devices.