SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• US 20070064482A1
• Filed: 09/20/2006
• Published: 03/22/2007
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken
• Granted Patent: US 7,411,819 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A semiconductor integrated circuit device has a first memory cell group including a plurality of rewritable nonvolatile memory cells arranged on a semiconductor chip and a second memory cell group including a plurality of rewritable nonvolatile memory cells arranged on the semiconductor chip. Setting of the write threshold voltage of the memory cell of the first memory cell group and setting of the write threshold voltage of the memory cell of the second memory cell group are variable.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor chip,

a first memory cell group containing a plurality of rewritable nonvolatile memory cells arranged on the chip, and

a second memory cell group containing a plurality of rewritable nonvolatile memory cells arranged on the chip,

wherein setting of write threshold voltages of the memory cells of the first memory cell group and setting of write threshold voltages of the memory cells of the second memory cell group are made variable.

2. The device according to claim 1, wherein the write threshold voltage is made variable by making variable step-up voltage width of a word line at write time.

3. The device according to claim 1, wherein the write threshold voltage is made variable by making variable write suppression voltage applied to a bit line.

4. The device according to claim 1, wherein the write threshold voltage is made variable by making variable word line voltage at verify read time.

5. The device according to claim 1, wherein word line voltage at read time of the first memory cell group and word line voltage at read time of the second memory cell group are made variable.

6. The device according to claim 1, wherein distribution width of the write threshold voltage of the first memory cell group is smaller than distribution width of the write threshold voltage of the second memory cell group.

7. The device according to claim 1, wherein the maximum write threshold voltage of the first memory cell group is lower than the maximum write threshold voltage of the second memory cell group.

8. The device according to claim 1, wherein the first and second memory cell groups configure a page.

9. The device according to claim 1, wherein the first and second memory cell groups configure a block.

10. The device according to claim 1, wherein the first and second memory cell groups configure a memory cell array.

11. The device according to claim 1, wherein the first and second memory cell groups are divided in the unit of one of each word line and a plurality of word lines.

12. The device according to claim 1, wherein gate length of the nonvolatile memory cell contained in the first memory cell group is different from gate length of the nonvolatile memory cell contained in the second memory cell group.

13. The device according to claim 1, wherein the first memory cell group is arranged adjacent to the selection gate line and gate length of the nonvolatile memory cell contained in the first memory cell group is different from gate length of the nonvolatile memory cell contained in the second memory cell group.

14. The device according to claim 1, wherein the first memory cell group is arranged adjacent to the selection gate line and gate length of the nonvolatile memory cell contained in the first memory cell group is the same as gate length of the nonvolatile memory cell contained in the second memory cell group.

15. The device according to claim 1, wherein setting contents of the threshold voltage are stored in the nonvolatile memory cell.

16. The device according to claim 1, wherein setting contents of the threshold voltage are read out before one of the write operation, read operation and erase operation and one of the word line voltage at write verify read time, the word line voltage at erase verify read time and the word line voltage at read time is made variable according to the readout result.

17. The device according to claim 1, wherein the plurality of rewritable nonvolatile memory cells are NAND nonvolatile memory cells.