Flash memory device and associated recharge method

• US 20070064512A1
• Filed: 07/17/2006
• Published: 03/22/2007
• Est. Priority Date: 09/21/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Chan-ho
• Granted Patent: US 7,403,420 B2
• Time in Patent Office: Days
• US Class Current: 365/218
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage line during a first program operation of the flash memory device, and then supplies a voltage from the second high voltage line to the first high voltage line during a second program operation.

Claims

1. A flash memory device, comprising:

a first high voltage line;

a second high voltage line; and

,

a switch circuit connected between the first and second high voltage lines and adapted to apply a program voltage apparent at the first high voltage line to the second high voltage line during a first program operation, and then apply a voltage apparent at the second high voltage line to the first high voltage line during a second program operation.

2. The flash memory device of claim 1, further comprising:

a pump circuit adapted to apply the program voltage to the first high voltage line and the second high voltage line.

3. The flash memory device of claim 2, wherein the switch circuit comprises:

a first switch controlled by a first enable signal and connected between the pump circuit and the first and second high voltage lines;

a second switch controlled by a second enable signal and connected between the first switch and the first high voltage line; and

,

a third switch controlled by a third enable signal and connected between the first switch and the second high voltage line.

4. The flash memory device of claim 3, wherein each of the first, second and third switches comprises:

a first inverter receiving a corresponding enable signal and having an output;

a second inverter connected between the output of the first inverter and having an output;

a first transistor having a source connected to the output of the second inverter, a gate receiving a power supply voltage, and a drain;

a second transistor having a source connected to the drain of the first transistor, a gate receiving the power supply voltage, and a source;

a third transistor having a source connected to a first terminal, a gate connected to the output of the first inverter, and a drain;

a fourth transistor having a source connected to the drain of the third transistor, a gate connected to the drain of the first transistor, and a drain;

a fifth transistor having a drain connected to the drain of the fourth transistor, a gate connected to the output of the second inverter, and a source connected to ground;

a sixth transistor having a source connected to the first terminal, a gate connected to the drain of the second transistor, and a drain;

a seventh transistor having a source connected to the drain of the sixth transistor, a gate connected to the drain of the fourth transistor, and a drain connected to the drain of the second transistor;

an eighth transistor having a source connected to the first terminal, and a gate connected to the drain of the second transistor, and a drain;

a ninth transistor having a source connected to the drain of the eighth transistor, a gate connected to the drain of the fourth transistor, and a drain; and

a tenth transistor having a source connected to the drain of the ninth transistor, a gate connected to the drain of the second transistor, and a drain connected to a second terminal.

5. The flash memory device of claim 4, wherein, in each of the first, second and third switches, the first transistor and the fifth transistor are NMOS transistors.

6. The flash memory device of claim 4, wherein, in each of the first, second and third switches, the second, third, sixth, eighth, and tenth transistors are depletion NMOS transistors.

7. The flash memory device of claim 4, wherein, in each of the first, second and third switches, the fourth, seventh, and ninth transistors are PMOS transistors.

8. A flash memory device having a 2-MAT structure comprising a plurality of block memory cell arrays, the flash memory device comprising:

a pump circuit adapted to generate a program voltage;

a first high voltage line connected between the pump circuit and a first MAT comprising a first plurality of memory blocks;

a second high voltage line connected to a second MAT comprising a second plurality of memory blocks;

a word line decoder connected to the first and second high voltage lines and adapted to drive the first and second pluralities of memory blocks with respective voltages apparent on the first and second high voltage lines; and

,

a switch circuit connected between the first and second high voltage lines and adapted to supply the program voltage from the first high voltage line to the second high voltage line during a first program operation, and then apply a voltage apparent at the second high voltage line to the first high voltage line during a second program operation.

9. The flash memory device of claim 8, wherein the first MAT or the second MAT selectively operates or the first MAT and the second MAT operate together, according to a data access width of the flash memory device.

10. The flash memory device of claim 8, wherein the pump circuit is adapted to generate and apply a read voltage to the first high voltage line and the second high voltage line.

11. The flash memory device of claim 8, wherein the switch circuit comprises:

a first switch controlled by a first enable signal and connected between the pump circuit and the first and second high voltage lines;

a second switch controlled by a second enable signal and connected between the first switch and the first high voltage line; and

,

a third switch controlled by a third enable signal and connected between the first switch and the second high voltage line.

12. The flash memory device of claim 11, wherein each of the first, second and third switches comprises:

a first inverter receiving a corresponding enable signal and having an output;

a second inverter connected between the output of the first inverter and having an output;

a first transistor having a source connected to the output of the second inverter, a gate receiving a power supply voltage, and a drain;

a second transistor having a source connected to the drain of the first transistor, a gate receiving the power supply voltage, and a source;

a third transistor having a source connected to a first terminal, a gate connected to the output of the first inverter, and a drain;

a fourth transistor having a source connected to the drain of the third transistor, a gate connected to the drain of the first transistor, and a drain;

a fifth transistor having a drain connected to the drain of the fourth transistor,

a gate connected to the output of the second inverter, and a source connected to ground;

a sixth transistor having a source connected to the first terminal, a gate connected to the drain of the second transistor, and a drain;

a seventh transistor having a source connected to the drain of the sixth transistor, a gate connected to the drain of the fourth transistor, and a drain connected to the drain of the second transistor;

an eighth transistor having a source connected to the first terminal, and a gate connected to the drain of the second transistor, and a drain;

a ninth transistor having a source connected to the drain of the eighth transistor, a gate connected to the drain of the fourth transistor, and a drain; and

a tenth transistor having a source connected to the drain of the ninth transistor, a gate connected to the drain of the second transistor, and a drain connected to a second terminal.

13. The flash memory device of claim 12, wherein, in each of the first, second and third switches, the first transistor and the fifth transistor are NMOS transistors.

14. The flash memory device of claim 12, wherein, in each of the first, second and third switches, the second, third, sixth, eighth, and tenth transistors are depletion NMOS transistors.

15. The flash memory device of claim 12, wherein, in each of the first, second and third switches, the fourth, seventh, and ninth transistors are PMOS transistors.

16. A method of recharging a flash memory device having a 2-MAT structure and comprising a plurality of memory blocks, the method comprising:

by operation of a pump circuit, generating a program voltage;

applying the program voltage to a first high voltage line connected to a first MAT to perform a first program operation;

upon completion of the first program operation, applying the program voltage from the first high voltage line to a second high voltage line connected to a second MAT;

applying a voltage apparent at the second high voltage line to the first high voltage line during a second program operation; and

,

by operation of the pump circuit, applying the program voltage to the first high voltage line during the second program operation.

17. The method of claim 16, wherein a switch circuit is connected between the pump circuit and the first and second high voltage lines.

18. The method of claim 17, wherein the switch circuit comprises:

a first switch controlled by a first enable signal and connected between the pump circuit and the first and second high voltage lines;

a second switch controlled by a second enable signal and connected between the first switch and the first high voltage line; and

,

a third switch controlled by a third enable signal and connected between the first switch and the second high voltage line.