Receive coalescing and automatic acknowledge in network interface controller

• US 20070064737A1
• Filed: 09/07/2005
• Published: 03/22/2007
• Est. Priority Date: 09/07/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Williams, James
• Granted Patent: US 8,311,059 B2
• Time in Patent Office: Days
• US Class Current: 370/473
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

An apparatus and method is disclosed for reducing the computational overhead incurred by a host processor during packet processing and improving network performance by adding additional functionality to a Network Interface Controller (NIC). Under certain circumstances the NIC coalesces multiple receive packets into a single coalesced packet stored within a coalesce buffer in host memory. The coalesced packet includes an Ethernet header, a coalesced Internet Protocol (IP) header, a coalesced Transmission Control Protocol (TCP) header, and a coalesced TCP payload containing the TCP payloads of the multiple receive packets. By coalescing received packets into fewer larger coalesced packets within the host memory, the host software needed to process a receive packet will be invoked less often, meaning that less processor overhead is incurred in the host.

Claims

1. A method for delivering a plurality of received packets from an input/output controller (IOC) to a host for processing, comprising:

determining that the plurality of received packets are part of a same connection;

determining that the plurality of received packets were received in order and without gaps;

combining headers and payloads of the plurality of received packets into a single coalesced packet if the plurality of received packets are part of the same connection and were received in order and without gaps; and

delivering the single coalesced packet to the host for processing.

2. The method as recited in claim 1, further comprising:

automatically acknowledging at least every other received packet in the IOC without host intervention.

3. The method as recited in claim 1, further comprising sending a coalesce command from the host to the IOC to cause the IOC to perform the steps recited in claim 1.

4. The method as recited in claim 1, further comprising determining that the plurality of received packets are part of a same connection by verifying that connection information contained in each of the plurality of received packets matches the connection information stored in the IOC.

5. The method as recited in claim 4, wherein the connection information includes an Ethertype, a source Internet Protocol (IP) address, a destination IP address, a protocol designation, a source port identifier, and a destination port identifier.

6. The method as recited in claim 4, further comprising:

determining if coalescing is enabled in the IOC; and

combining the headers and payloads of the plurality of received packets into a single coalesced packet only if coalescing is enabled in the IOC.

7. The method as recited in claim 6, further comprising determining if coalescing is enabled in the IOC by reading a receive coalesce enable bit.

8. The method as recited in claim 1, further comprising determining that the plurality of received packets were received in order and without gaps by verifying that a sequence number contained in each of the plurality of received packets matches a next expected sequence value stored in the IOC.

9. The method as recited in claim 1, further comprising reading a host buffer pointer and a host buffer offset to determine a location for storing a received packet to be combined into the single coalesced packet.

10. The method as recited in claim 2, further comprising reading an acknowledge next bit to determine whether to acknowledge a received packet to be combined into the single coalesced packet.

11. The method as recited in claim 1, each packet in the plurality of packets including a first protocol header, a second protocol header, a third protocol header, and a third protocol payload, the method further comprising:

combining the second protocol headers of the plurality of packets into a single coalesced second protocol header in the coalesced packet;

combining the third protocol headers of the plurality of packets into a single coalesced third protocol header in the coalesced packet; and

combining the third protocol payloads of the plurality of packets into a single coalesced third protocol payload in the coalesced packet.

12. The method as recited in claim 11, further comprising:

storing a sum of third protocol payload lengths for each packet in the plurality of packets into a length field in the coalesced second protocol header.

13. The method as recited in claim 11, wherein the first protocol header is an Ethernet header, the second protocol header is an Internet Protocol (IP) header, the third protocol header is a Transmission Control Protocol (TCP) header, and the third protocol payload is a TCP payload.

14. The method as recited in claim 1, wherein the input/output controller is a Network Interface Controller (NIC).

15. The method as recited in claim 1, further comprising stopping the combining of the headers and payloads of the plurality of received packets into a single coalesced packet if the host sends a stop coalesce command to the IOC or if a packet is received out of sequence.

16. The method as recited in claim 1, further comprising delivering the single coalesced packet to the host for processing when the coalesced packet fills up a host buffer within which the coalesced packet is being stored.

17. An input/output controller (IOC) for delivering a plurality of received packets to a host for processing, comprising:

a local memory for storing received packets, connection information and connection state information; and

a controller and compare/control logic coupled to the local memory and configured for

comparing connection information located in the plurality of received packets to the connection information stored in the local memory to determine whether the plurality of received packets are part of a same connection,

comparing sequence numbers located in the plurality of received packets to next expected sequence values stored in the local memory as part of the connection state information to determine whether the plurality of received packets were received in order and without gaps, and

sending commands to the host for updating a single coalesced packet stored in the host with header and payload information from the plurality of received packets if the plurality of received packets are part of the same connection and were received in order and without gaps.

18. The IOC as recited in claim 17, the local memory for storing acknowledgement information, the controller and compare/control logic further configured for automatically acknowledging at least every other received packet in the IOC without host intervention when indicated by the acknowledgement information.

19. The IOC as recited in claim 17, the controller and compare/control logic further configured for starting coalescing when a coalesce command is received from the host.

20. The IOC as recited in claim 17, wherein the connection information stored in the local memory includes an Ethertype, a source Internet Protocol (IP) address, a destination IP address, a protocol designation, a source port identifier, and a destination port identifier.

21. The IOC as recited in claim 17, the local memory for storing a receive coalesce enable bit, the controller and compare/control logic further configured for:

determining if coalescing is enabled in the IOC by reading the receive coalesce enable bit; and

sending commands to the host for updating a single coalesced packet stored in the host with header and payload information from the plurality of received packets only if coalescing is enabled in the IOC.

22. The IOC as recited in claim 17, the local memory for storing a host buffer pointer and a host buffer offset, the controller and compare/control logic further configured for reading the host buffer pointer and the host buffer offset to determine a location for storing a received packet to be combined into the single coalesced packet.

23. The IOC as recited in claim 17, the local memory for storing an acknowledge next bit, the controller and compare/control logic further configured for reading the acknowledge next bit to determine whether to acknowledge a received packet to be combined into the single coalesced packet.

24. The IOC as recited in claim 17, each packet in the plurality of received packets including a first protocol header, a second protocol header, a third protocol header, and a third protocol payload, the controller and compare/control logic further configured for sending commands to the host for updating a single coalesced packet stored in the host by:

combining the second protocol headers of the plurality of packets into a single coalesced second protocol header in the coalesced packet;

combining the third protocol headers of the plurality of packets into a single coalesced third protocol header in the coalesced packet; and

combining the third protocol payloads of the plurality of packets into a single coalesced third protocol payload in the coalesced packet.

25. The IOC as recited in claim 24, the controller and compare/control logic further configured for storing a sum of third protocol payload lengths for each packet in the plurality of packets into a length field in the coalesced second protocol header.

26. The IOC as recited in claim 24, wherein the first protocol header is an Ethernet header, the second protocol header is an Internet Protocol (IP) header, the third protocol header is a Transmission Control Protocol (TCP) header, and the third protocol payload is a TCP payload.

27. The IOC as recited in claim 17, wherein the input/output controller is a Network Interface Controller (NIC).

28. The IOC as recited in claim 17, the controller and compare/control logic further configured for stopping the combining of the headers and payloads of the plurality of received packets into a single coalesced packet if the host sends a stop coalesce command to the IOC or if a packet is received out of sequence.

29. The IOC as recited in claim 17, the controller and compare/control logic further configured for delivering the single coalesced packet to the host for processing when the coalesced packet fills up a host buffer within which the coalesced packet is being stored.

30. A server comprising a host and the IOC as recited in claim 17.

31. A Storage Area Network (SAN) comprising the server as recited in claim 30.

32. One or more storage media including a computer program which, when executed by one or more processors in an Input/Output Controller (IOC), assists in delivering a plurality of received packets from the IOC to a host for processing by causing the one or more processors to perform the steps of:

determining that the plurality of received packets are part of a same connection;

determining that the plurality of received packets were received in order and without gaps; and

sending commands to the host for updating a single coalesced packet stored in the host with header and payload information from the plurality of received packets if the plurality of received packets are part of the same connection and were received in order and without gaps.

33. The one or more storage media as recited in claim 32, wherein the computer program, when executed by one or more processors, further causes the one or more processors to perform the step of automatically acknowledging at least every other received packet in the IOC without host intervention.