Thin film transistor array panel and method of manufacturing the same

• US 20070065991A1
• Filed: 09/16/2004
• Published: 03/22/2007
• Est. Priority Date: 09/18/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sung-Chul, Kim, Sang-Gab, Choi, Joon-Hoo, Choi, Beohm-Rock, Song, In-Ho, Choe, Hee-Hwan, Kang, Ho-Min, Jeong, Jong-Tae, Lee, Je-Min, Cho, Gwan-Young
• Granted Patent: US 7,482,208 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H10K 2102/351 Thickness
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/38 comprising colour filters or colour changing media [CCM]

Abstract

The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a first signal line formed on the insulating substrate and extending in a first direction;

a first insulating layer formed on the first signal line;

a second signal line formed on the first insulating layer and intersecting the first signal line;

a thin film transistor connected to the first and second signal lines;

a second insulating layer formed on the thin film transistor and having a first contact hole exposing a terminal of the thin film transistor; and

a pixel electrode formed on the second insulating layer, connected to the thin film transistor through the first contact hole, and having a structure of double layers including IZO layer and ITO layer.

2. The thin film transistor array panel of claim 1, wherein the IZO layer has a thickness of 500 Å

to 1500 Å and

the ITO layer has a thickness of 50 Å

to 250 Å

.

3. The thin film transistor array panel of claim 2, wherein the thickness of the IZO layer is 900 Å

and the thickness of the ITO layer is 200 Å

.

4. The thin film transistor array panel of claim 1, further comprising a color filter disposed in a pixel region that is defined by intersection of the first and second signal lines and covered by the second insulating layer.

5. The thin film transistor array panel of claim 1, wherein the second insulating layer has a second contact hole exposing an expansion of the first signal line and a third contact hole exposing an expansion of the second signal line, and further comprising:

a first contact assistant connected to the expansion of the first signal line through the second contact hole; and

a second contact assistant connected to the expansion of the second signal line through the second contact hole.

6. The thin film transistor array panel of claim 5, wherein the first and second contact assistants have a structure of double layer including IZO layer and ITO layer.

7. A thin film transistor array panel comprising:

a gate line formed on a insulating substrate and including a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor formed on the gate insulating layer;

a data line including a source electrode and intersecting the gate line to define a pixel region;

a drain electrode facing the source electrode with a gap therebetween on the semiconductor;

a passivation layer having a first contact hole exposing the drain electrode;

a pixel electrode, formed on the passivation layer, connected to the drain electrode through the first contact hole, and having a structure of double layers including IZO layer and ITO layer.

8. The thin film transistor array panel of claim 7, further comprising a storage capacitor conductor overlapping the gate line or a storage electrode line formed on the same layer with the gate line.

9. The thin film transistor array panel of claim 8, wherein the storage capacitor conductor connected with the drain electrode.

10. The thin film transistor array panel of claim 7, wherein the passivation layer is made of a chemical vapor deposition layer having a dielectric constant lower than 4.0 or an acrylic organic material.

11. The thin film transistor array panel of claim 7, wherein the semiconductor has substantially the same pattern with the data line and the drain electrode except for a channel region between the source electrode and the drain electrode.

12. The thin film transistor array panel of claim 7, wherein further comprising a color filter disposed in a pixel and covered by the second insulating layer.

13. The thin film transistor array panel of claim 7, wherein the IZO layer has a thickness of 500 Å

to 1500 Å and

the ITO layer has a thickness of 50 Å

to 250 Å

.

14. The thin film transistor array panel of claim 13, wherein the thickness of the IZO layer is 900 Å

and the thickness of the ITO layer is 200 Å

.

15. The thin film transistor array panel of claim 7, wherein the passivation layer has a second contact hole exposing an expansion of the gate line and a third contact hole exposing an expansion of the data line, and further comprising:

a first contact assistant connected to the expansion of the gate line through the second contact hole; and

a second contact assistant connected to the expansion of the data through the second contact hole.

16. The thin film transistor array panel of claim 15, wherein the first and second contact assistants have a structure of double layer including IZO layer and ITO layer.

17. A method of manufacturing a thin film transistor array panel comprising:

forming a gate line including a gate electrode on an insulating substrate;

forming a gate insulating layer covering the gate line;

forming a semiconductor on the gate insulating layer;

forming a data line including a source electrode and intersecting the gate line and a drain electrode separated from and opposite to the source electrode with respect to the gate electrode;

depositing a passivation layer;

patterning the passivation layer along with the gate insulating layer to form contact holes exposing an expansions of the gate line and the data line and the drain electrode;

depositing IZO layer and ITO layer in sequence; and

photo-etching the IZO layer and ITO layer to form a pixel electrode and contact assistants respectively connected to the drain electrode and the expansions of the gate line and the data line,

wherein the IZO layer and the ITO layer are etched by an IZO etchant containing HCl.

18. The method of claim 17, wherein the IZO etchant contains HCl, CH₃COOH, deionized water, and a surfactant.

19. The method of claim 17, wherein the data line and the semiconductor are formed by a photo-etching process that use a photoresist pattern having a first portion, a second portion thicker than the first portion, and a third portion thinner than the first portion.

20. The method of claim 19, wherein the first portion is disposed on the region between the source electrode and the drain electrode and the second portion is disposed on the data line and the drain electrode.

21. A method of manufacturing a thin film transistor array panel comprising:

forming a gate line including a gate electrode on an insulating substrate;

forming a gate insulating layer covering the gate line;

forming a semiconductor on the gate insulating layer;

forming a data line including a source electrode and a drain electrode separated from and opposite to the source electrode on the gate insulating layer;

forming color filters on the data line using photoresist material including pigment of red, green, and blue, the color filter having a first opening exposing at least a portion of the drain electrode;

depositing a passivation layer on the color filter;

patterning the passivation layer to form a first contact hole within the first opening to expose at least a portion of the drain electrode; and

forming a pixel electrode connected to the drain electrode via the first contact hole,

wherein the step of forming the pixel electrode comprises depositing IZO layer and ITO layer in sequence and photo-etching the IZO layer and the ITO layer with an IZO etchant containing HCl.

22. The method of claim 21, further comprising a step of forming an interlayer insulating layer of silicon nitride or silicon oxide before the step of forming color filters.

23. The method of claim 21, wherein the IZO etchant contains HCl, CH₃COOH, deionized water, and a surfactant.

24. A thin film transistor array panel comprising:

a gate line formed on a insulating substrate and including a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor formed on the gate insulating layer;

a data line including a source electrode and intersecting the gate line to define a pixel region;

a drain electrode formed on the same layer with the data line and facing the source electrode with a gap therebetween;

a passivation layer having a first contact hole exposing the drain electrode;

a pixel electrode formed on the passivation layer, connected to the drain electrode through the first contact hole;

contact assistants for connecting the expansions of the gate line and the data line to an external circuit,

wherein the contact assistants have a structure of double layers including IZO layer and ITO layer.

25. The thin film transistor array panel of claim 24, wherein the ITO layer is disposed on the IZO layer.

26. A liquid crystal display comprising:

a thin film transistor array panel comprising a gate line formed on a insulating substrate and including a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor formed on the gate insulating layer;

a data line including a source electrode and intersecting the gate line to define a pixel region;

a drain electrode formed on the same layer with the data line and facing the source electrode with a gap therebetween;

a passivation layer having a first contact hole exposing the drain electrode;

a pixel electrode formed on the passivation layer, connected to the drain electrode through the first contact hole;

contact assistants for connecting the expansions of the gate line and the data line to an external circuit, wherein the contact assistants have a structure of double layers including IZO layer and ITO layer;

a color filter array panel facing the thin film transistor panel and comprising a common electrode; and

a liquid crystal layer interposed between the thin film transistor panel and the color filter panel.

27. A method of manufacturing a liquid crystal display comprising:

forming a gate line including a gate electrode on an first insulating substrate;

forming a gate insulating layer covering the gate line;

forming a semiconductor on the gate insulating layer;

forming a data line including a source electrode and a drain electrode separated from and opposite to the source electrode on the gate insulating layer;

forming a passivation layer having a first contact hole exposing the drain electrode;

forming a pixel electrode connected to the drain electrode via the first contact hole and, contact assistants connecting the drain electrode and expansions of the gate line and the data line to an external circuit;

forming a common electrode on a second insulating substrate;

injecting liquid crystal material between the first substrate and the second substrate and sealing the liquid crystal material; and

forming ITO layer on the contact assistants.

28. The method of claim 27, wherein the ITO layer is formed on the contact assistants by using a shadow mask having openings corresponding to the contact assistants.

29. The method of claim 27, wherein the ITO layer is formed on the contact assistants by evaporation.

30. The method of claim 27, wherein the evaporation is performed after all of the processes, assembling of the first substrate and the second substrate, injection of liquid crystal material, and cutting mother panels into cells.

31. A thin film transistor array panel comprising:

a first and second semiconductors respectively having a first and second channel portions formed on an insulating substrate;

a gate line including a first gate electrode that overlaps the first channel portion;

a second gate electrode overlapping the second channel portion;

a gate insulating layer disposed between the first and second semiconductors and the first and second gate electrodes;

a data line including a first source electrode contacting with the first semiconductor;

a first drain electrode facing the first source electrode and connected to the second gate electrode, the first channel portion is disposed between the first drain electrode and the first source electrode;

a second source electrode adjoining the second channel portion;

a second drain electrode adjoining the second channel portion and facing the second source electrode with respect to the second channel portion;

a pixel electrode connected to the second drain electrode and disposed on a pixel region surrounded by the gate line and the data line;

a partitioning wall having opening exposing the pixel electrode;

a subsidiary electrode formed on the partitioning wall and having substantially the same pattern with the partitioning wall;

an organic luminescence layer formed on the pixel electrode and filled in the opening of the partitioning wall;

a common electrode covering the subsidiary electrode and the organic luminescence layer; and

contact assistants connected to expansions of the gate line and the data line,

wherein the contact assistants have a structure of double layer including IZO layer and ITO layer.

32. The thin film transistor array panel of claim 31, wherein the ITO layer is disposed on the IZO layer

33. The thin film transistor array panel of claim 31, wherein the pixel electrode has a structure of double layers including IZO layer and ITO layer.

34. The thin film transistor array panel of claim 33, the ITO layer of the pixel electrode is disposed on the IZO layer of the pixel electrode.

35. A method of manufacturing a thin film transistor array panel comprising:

forming a first and second semiconductors made of polysilicon or amorphous silicon on an insulating substrate;

forming a gate line including a first gate electrode and a second gate electrode;

forming a gate insulating layer disposed between the first and second semiconductors and the first and second gate electrodes;

forming a first and second source electrodes, a data line, a first and second drain electrodes, and a power line on the gate insulating layer;

forming an interlayer insulating layer covering the first and second source electrodes, the data line, the first and second drain electrodes, and the power,

forming a pixel electrode connected to the second drain electrode and contact assistants connected to expansions of the gate line and the data line on the interlayer insulating layer;

forming a partitioning wall having an opening for exposing the pixel electrode;

forming a subsidiary electrode on the partitioning wall;

forming an organic luminescence layer on the pixel electrode to fill the opening of the partitioning wall; and

forming a common electrode on the subsidiary electrode and the organic luminescence layer,

wherein the contact assistants have a structure of double layer including IZO layer and ITO layer.

36. The method of claim 35, wherein the ITO layer is disposed on the IZO layer.

37. The method of claim 36, wherein the pixel electrode has a structure of double layers including IZO layer and ITO layer.

38. The method of claim 37 the ITO layer of the pixel electrode is disposed on the IZO layer of the pixel electrode.

39. A thin film transistor array panel comprising:

an insulating substrate;

a blocking layer formed on the insulating substrate;

a polysilicon layer formed on the blocking layer;

a gate insulating layer formed on the polysilicon layer;

a gate line formed on the gate insulating layer;

a first interlayer insulating layer formed on the gate line;

a first and a second contact holes formed in the first interlayer insulating layer and exposing a source region and a drain region of the polysilicon layer;

a data line including a source electrode connected to the source region though the first contact hole;

a drain electrode connected to the drain region through the second contact hole;

a second interlayer insulating layer formed on the data line and the drain electrode and having a third contact hole exposing the drain electrode;

a pixel electrode formed on the second interlayer insulating layer, connected to the drain electrode through the third contact hole, and having a structure of double layers including IZO layer and ITO layer.

40. The thin film transistor array panel of claim 39, wherein the first and second interlayer insulating layers have a fourth contact hole exposing an expansion of the gate line and the second interlayer insulating layer has a fifth contact hole exposing an expansion of the date line,

further comprising:

a first contact assistant connected to the expansion of the gate line through the fourth contact hole and having a structure of double layer including IZO layer and ITO layer; and

a second contact assistant connected to the expansion of the data line through the fifth contact hole and having a structure of double layer including IZO layer and ITO layer.

41. The thin film transistor array panel of claim 39 or claim 40, wherein the ITO layer is disposed on the IZO layer.