Method for manufacturing substrate with cavity

• US 20070066045A1
• Filed: 09/21/2006
• Published: 03/22/2007
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kang, Myung, Jung, Hoe, Park, Jung
• Granted Patent: US 7,498,205 B2
• Time in Patent Office: Days
• US Class Current: 438/613
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2203/0769 : Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
• CPC Class Codes: H05K 2203/308 : Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence

Abstract

A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master; (b) coating a thermosetting material in the area where the cavity is to be formed; (c) laminating a dielectric layer and a copper foil layer on the copper foil laminated master, on which the thermosetting material is coated; (d) pressing the laminated dielectric layer and copper foil layer using a press plate, on which a protruded part is formed in an area corresponding to the area where the cavity is to be formed; (e) forming an external circuit pattern in the upper part of the laminated dielectric layer; and (f) dissolving the coated thermosetting material using a solvent and forming the cavity. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

Claims

1. A method for manufacturing a substrate, the substrate having a cavity, the method comprising:

(a) forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master;

(b) coating a thermosetting material in the area where the cavity is to be formed;

(c) laminating a dielectric layer and a copper foil layer on the copper foil laminated master, on which the thermosetting material is coated;

(d) pressing the laminated dielectric layer and copper foil layer using a press plate, on which a protruded part is formed in an area corresponding to the area where the cavity is to be formed;

(e) forming an external circuit pattern in the upper part of the laminated dielectric layer; and

(f) dissolving the coated thermosetting material using a solvent and forming the cavity.

2. The method of claim 1, wherein the dielectric layer and copper foil layer are a resin coated copper foil or the dielectric layer is a prepreg.

3. The method of claim 1, wherein the barrier is printed by use of a screen method or by exposing a thermosetting film.

4. The method of claim 1, wherein the glass transition temperature (Tg) of the thermosetting material is higher than the glass transition temperature (Tg) of the dielectric layer.

5. The method of claim 1, wherein the thermosetting material does not mix with the dielectric layer.

6. The method of claim 1, further comprising (g) depositing in the formed cavity a bonding pad for electrically connecting an element and the substrate, by use of electrolytic plating or electroless plating.