Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization

• US 20070067518A1
• Filed: 09/09/2005
• Published: 03/22/2007
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: Ademco Inc. (Resideo Technologies, Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Nichols, Steven
• Granted Patent: US 7,769,932 B2
• Time in Patent Office: Days
• US Class Current: 710/100
• CPC Class Codes: H04J 3/0641 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 5/02 Channels characterised by the type of signal

Abstract

A plurality of nodes are coupled via a serial data bus so that simultaneous transmission on the bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the bus. A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes. The first and second states are complementary states selected from the dominant and recessive states. The arbitrarily selected node is defined as the bit master. One or more of the nodes transmits onto the bus dominant and recessive states at a first predetermined time after each transition. The transmitted states representing respective dominant and recessive bits of an attempted message. The plurality of nodes detect dominant and recessive states of the bus at a second predetermined time after each transition. The sensed dominant and recessive states representing respective dominant and recessive bits of a detected message. Any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time ceases transmission of bits onto the bus.

Claims

1. A method of communicating between a plurality of nodes coupled via a serial data bus so that simultaneous transmission on the bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the bus, the method comprising:

repeatedly transmitting onto the bus a transition from a first state to a second state from a node arbitrarily selected from the plurality of nodes, wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the arbitrarily selected node is defined as the bit master;

transmitting onto the bus dominant and recessive states from one or more of the nodes at a first predetermined time after each transition, the transmitted states representing respective dominant and recessive bits of an attempted message;

detecting, at the plurality of nodes, dominant and recessive states of the bus at a second predetermined time after each transition, the sensed dominant and recessive states representing respective dominant and recessive bits of a detected message; and

ceasing transmission of bits onto the bus by any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time.

2. The method of claim 1, further comprising,

for each node of the plurality of nodes, measuring a timeout value between successive transitions from the first signal level to the second signal level onto the bus as transmitted by the bit master;

and

if the timeout value exceeds a predetermined value, repeatedly transmitting onto the bus a transition from the first signal level to the second signal level by a second node arbitrarily selected from the plurality of nodes that are not defined as the bit master, wherein the second arbitrarily selected node is thereafter defined as the bit master.

3. The method of claim 1, further comprising transmitting the first signal level on to the bus by the bit master at a third predetermined time after each transition, the third predetermined time occurring after the second predetermined time.

4. The method of claim 1, wherein repeatedly transmitting onto the bus the transition from the first state to the second state from the bit master comprises repeatedly transmitting onto the bus a transition from the dominant state to the recessive state.

5. The method of claim 1, wherein the transmitting the dominant and recessive states comprise asserting respective first and second voltages on the bus, wherein the second voltage is higher than the first voltage.

6. The method of claim 5, wherein repeatedly transmitting onto the bus the transition from the first state to the second state comprises transmitting on the bus from the first voltage to the second voltage.

7. The method of claim 6, wherein repeatedly transmitting onto the bus the transition from the first voltage to the second voltage comprises transmitting the second voltage using a strong current sufficient to assert the second voltage when the first voltage is present on the bus, and wherein transmitting onto the bus recessive states representing respective recessive bits of the attempted message comprises transmitting the second voltage using a weak current that is sufficient to maintain the second voltage on the bus only if the second voltage is already present on the bus.

8. The method of claim 1, further comprising ceasing repeated transmission of the transition from the first state to the second state onto the bus by the bit master if the bit master does not simultaneously detect the transition while the bit master is transmitting the transition.

9. The method of claim 1, further comprising ceasing repeated transmission of the transition from the first state to the second state onto the bus by the bit master if the bit master detects a transition from the first state to the second state that the bit master did not transmit.

10. The method of claim 1, wherein the bit master is capable of repeatedly transmitting the transition onto the data bus at a time period that is substantially greater than a minimum allowable time period supported by the nodes.

11. The method of claim 10, further comprising, for each of the nodes, entering an extended bit mode if the time period satisfies a threshold value.

12. A node operable in a data processing arrangement that includes a plurality of nodes that are capable of communicating with one another via a serial data bus, the node comprising:

a transceiver capable of transmitting and receiving a dominant state and a recessive state on the bus, wherein simultaneous transmission of the dominant state on the bus by at least one of the plurality of nodes and transmission of the recessive state on the bus by any other of the plurality of nodes results in the dominant state being detectable on the bus;

a bit master module capable of detecting, via the transceiver, repeated transitions from a first state to a second state on the bus, wherein the first and second states are complementary states selected from the dominant and recessive states, the bit master module causing the transceiver to repeatedly transmit on to the bus the transitions from the first state to the second state if the bit master module detects none of the plurality of nodes transmitting the transition;

a message module causing the transceiver to transmit on the bus a message comprising a series of bits, wherein each bit the message is transmitted by causing the transceiver to,

detect via the transceiver each transition from the first state to the second state on the bus;

transmit either of the dominant state or recessive state onto the serial bus at a first predetermined time after each transition, the transmitted state representing intended values of a current bit being sent by the node;

detect a state of the bus at a second predetermined time after each transition, the detected state representing an actual value of the current bit on the bus; and

ceasing transmission of bits onto the bus if the node transmits the recessive state and detects the dominant state.

13. The node of claim 12, wherein the bit master module is further configured to:

measure a timeout value between successive transitions detected on the bus via the transceiver; and

repeatedly transmit the transitions onto the bus if the timeout value exceeds a predetermined value.

14. The node of claim 12, wherein the bit master module is further configured to:

cease repeated transmission of the transitions from the first state to the second state onto the bus if, while the bit master is transmitting the transitions on to the bus via the transceiver, the bit master module does not simultaneously detect the transitions via the transceiver.

15. The node of claim 12, wherein the first state comprises the dominant state, and the second state comprises the recessive state.

16. The node of claim 15, wherein the dominant and recessive states comprise respective first and second voltages, wherein the second voltage is higher than the first voltage.

17. The node of claim 16, wherein the transceiver further comprises:

a weak current pullup circuit that provides sufficient current to maintain the second voltage on the bus only if the second voltage is already present on the bus; and

a strong current pullup circuit that provides sufficient current to assert the second voltage on the bus if the first voltage is present on the bus; and

wherein the bit master module causes the transceiver to transmit the second voltage using the strong current pullup circuit when transmitting the transition on to the bus, and wherein the message module causes the transceiver to transmit the second voltage using the weak current pullup circuit when transmitting onto the bus recessive states corresponding to recessive bits of a transmitted message.

18. The node of claim 16, wherein the bit master module is further configured to transmit the first voltage on to the bus for a time period just preceding each transition.

19. The node of claim 12, further comprising an application module configured to utilize messages received via the message module.

20. The node of claim 19, wherein the application module is to enter an extended bit mode when the application module determines that a time period between successive transitions on the bus satisfies a threshold value.

21. The node of claim 12, wherein the node is configured to operate in a heating, ventilation, and air conditioning (HVAC) system.

22. A system, comprising:

a serial bus; and

a plurality of nodes coupled via the serial bus so that simultaneous transmission on the bus of a dominant state by one of the nodes and a recessive state by any other of the nodes results in the dominant state being detectable on the bus, wherein one or more of the plurality of nodes are configured as bit master capable nodes, the bit master capable nodes including,

means for detecting on the bus transitions from a first state to a second state, wherein the first and second states are complementary states selected from the dominant and recessive states; and

means for repeatedly transmitting onto the bus the transitions from the first to second state if the bit master capable node detects none of the plurality of nodes transmitting the transition; and

wherein each node of the plurality of nodes includes,

means for transmitting onto the bus dominant and recessive states at a first predetermined time after each transition, the transmitted states representing respective dominant and recessive bits of an attempted message sent by the node;

means for detecting states of the bus at a second predetermined time after each transition, the detected states representing respective dominant and recessive bits of a detected message; and

means for ceasing transmission of bits onto the bus if a recessive bit is transmitted and a dominant bit is detected.

23. The system of claim 22, wherein the bit master capable nodes further comprise:

means for measuring a timeout value between successive transitions from the first state to the second state; and

means for repeatedly transmitting the transitions onto the bus if the timeout value satisfies a predetermined value.

24. The system of claim 22, wherein each node of the plurality of nodes further comprises:

means for measuring time periods between successive transitions onto the bus; and

means for entering into an extended bit state if the measured time periods satisfy a threshold value that is greater than a minimum time period supported by the nodes.

25. A processor-readable medium, comprising:

a program storage device configured with instructions for causing a processor of a node coupled to a plurality of nodes coupled via a serial bus so that simultaneous transmission on the bus of a dominant state by one of the nodes and a recessive state by any other of the nodes results in the dominant state being detectable on the bus, the instructions causing the processor to perform the operations of,

detecting on the bus transitions from a first state to a second state, wherein the first and second states are complementary states selected from the dominant and recessive states;

repeatedly transmitting onto the bus the transitions from the first to second state if the node detects none of the plurality of nodes transmitting the transition;

transmitting onto the bus dominant and recessive states at a first predetermined time after each transition, the transmitted states representing respective dominant and recessive bits of an attempted message;

detecting states of the bus at a second predetermined time after each transition; and

ceasing transmission of bits onto the bus if the node transmits a recessive bit and detects a dominant bit at the second predetermined time.