APPARATUS AND METHOD FOR MEMORY BIT-SWAPPING-WITHIN-ADDRESS-RANGE CIRCUIT

• US 20070067556A1
• Filed: 11/10/2006
• Published: 03/22/2007
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Snyder, Van, Resnick, David, Dixon, R.
• Granted Patent: US 7,565,593 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Claims

1. An information-processing apparatus comprising:

a first memory having a plurality of addressed locations, each location holding a plurality of bits; and

a first control circuit, wherein the first control circuit includes;

a first memory controller coupled to the first memory, the memory controller including;

a read-bit-swap circuit coupled to receive data from the first memory, the read-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each read bit is coupled to one input on each of two non-adjacent multiplexers;

a write-data bit-swap circuit coupled to transmit data to the first memory, the write-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each bit to be written is coupled to one input on each of two non-adjacent multiplexers; and

a swap-controller circuit operatively coupled to the read-bit-swap circuit and to the write-data bit-swap circuit to selectively choose one or more spare bits in place of a corresponding number of other bits.

2. The apparatus of claim 1, the first memory controller further comprising an address-range detector that specifies a range spanning a subset of the addressed locations, and for each memory request, that determines whether an address of the memory request is within the specified range and that is coupled to control the read-bit-swap circuit and the write-bit-swap circuit.

3. The apparatus of claim 2, the first memory controller further comprising an address incrementer operatively coupled to address-range detector to adjust an end of the specified range.

4. The apparatus of claim 2, the first memory controller further comprising a section-swap controller operatively coupled to initialize the address range detector and address incrementer to, for each location within a section of memory, control an atomic read-write operation that reads data from the location in memory using a first bit-mapping configuration and to writes data back to the location in memory using a second bit-mapping configuration different than the first.

5. The apparatus of claim 4, the first memory controller further comprising an error-correction circuit that, for at least some of the atomic read-write operations, corrects an error in the read data and generates corrected data for the write.

6. The apparatus of claim 5, the first memory controller further comprising a processor memory-request controller that, interleaved between the atomic read-write operations, performs processor memory operations both within the specified range and outside of the specified range.

7. The apparatus of claim 6, further comprising a memory-request buffer configured to hold a plurality of pending memory requests, wherein the error-correction circuit corrects errors based on an error-correction code (ECC), and wherein, for each atomic read-write operation, the section-swap controller operates to inhibit conflicting operations from the memory-request buffer during each read-swap-write operation while allowing non-conflicting operations in the buffer to be processed.

8. The apparatus of claim 6, further comprising a memory-request buffer configured to hold a plurality of pending memory requests, wherein the error-correction circuit corrects errors based on a SECDED ECC, and wherein, for each atomic read-write operation, the section-swap controller operates to inhibit operations from the memory-request buffer and to prevent further memory requests from being accepted for a period of time to allow the atomic read-write operation to effectively complete.

9. The apparatus of claim 7, further comprising a refresh controller, coupled to the memory-request buffer, and configured to send read-refresh requests, the read-refresh requests using refresh addresses that cycle through address bits for a row-address portion of the refresh address and also cycle through bits for the column-address portion of the refresh address, and wherein read-refresh data is fetched to the memory-chip interface and checked by an error detector as a result of each of the read-refresh requests.

10. The apparatus of claim 9, the read-refresh data is used as the basis for the bit-swap operation.

11. The apparatus of claim 9, wherein the refresh controller is further configured to send explicit-refresh requests to the memory-request buffer, wherein the explicit-refresh requests are sent to the memory chips to cause the memory chips to perform an internally controlled refresh function.

12. The apparatus of claim 11, wherein the refresh controller further includes a timer controller that allows the timing between explicit-refresh requests to be varied.

13. The apparatus of claim 9, wherein the refresh controller further includes a priority controller that sends a first read-refresh request at an initial priority value, and later if the first read-refresh request has not been completed, increases the priority value.

14. The apparatus of claim 1, the first control circuit further including a test engine operatively coupled to the first memory controller and configured to provide test functions to verify whether, for memory requests having addresses within the range, the one or more bits are swapped, wherein the first control circuit is located on a first memory card, and the test engine is located on a second memory card that is substantially identical to the first memory card.

15. The apparatus of claim 1, further comprising:

a plurality of high-speed serial external interfaces;

a second memory controller substantially the same as the first memory controller;

a second memory operatively coupled to the second memory controller; and

a crossbar switch operatively coupled to transmit and receive memory commands and data to and from the first and second memory controllers, and to and from the plurality of high-speed serial external interfaces.

16. The apparatus of claim 15, wherein the apparatus is packaged on a single first memory card.

17. The apparatus of claim 16, further comprising:

a second memory card substantially the same as the first memory card;

a first plurality of processors coupled to the first memory card and to the second memory card;

a third and fourth memory card each substantially the same as the first memory card;

a second plurality of processors coupled to the third memory card and to the fourth memory card;

a network operatively coupled between the first plurality of processors and the second plurality of processors; and

an input/output system operatively coupled to provide data to and from the first plurality of processors.

18. The apparatus of claim 16, further comprising:

a first plurality of processors coupled to the plurality of high-speed serial external interfaces;

a network operatively coupled to each of the first plurality of processors;

an input/output system operatively coupled to provide data to and from the first plurality of processors; and

a power supply operatively coupled to provide power to the first plurality of processors.

19. An information-processing method comprising:

receiving a first memory request that specifies a first address;

detecting whether the first address of the first memory request is within a specified range of addresses;

 

and if the first memory request is for one or more write operations;

shifting a first subset of bit positions a plurality of bit positions in a first direction for first data of each write operation address being detected as within the specified range, and

writing the bit-swapped first data to the memory;

 

and if the first memory request is for one or more read operations;

reading second data from the memory, and

shifting a second subset of bit positions a plurality of bit positions in a second direction opposite the first direction for each read operation address being detected as within the specified range.

20. The method of claim 19, further comprising performing an atomic read-write operation that includes a second memory read request from a second address and a third memory write request to the second address.

21. The method of claim 20, further comprising:

changing an end address of the specified range between the second and third memory requests of the atomic read-write operation; and

bit swapping such that data based on the read second data is bit-swapped to produce the first data and written to its same address.

22. The method of claim 20, wherein the first memory request performs the function of read-refreshing one or more locations in memory and obtains read-refresh data from the second address, the method further comprising:

using the read-refresh data as the basis for the bit-swapping.

23. The method of claim 21, further comprising performing error correction on the read data before bit swapping and writing.

24. The method of claim 23, further comprising iteratively changing the end address and reading and writing data in a section of the memory in order to dynamically move data in the section of the memory from a normal bit mapping configuration to a bit-swapped mapping configuration.

25. The method of claim 23, further comprising:

buffering a first plurality of pending memory requests from a processor;

sending a stream of the first processor memory requests from the buffered pending memory requests to the memory; and

stopping servicing of processor memory requests in order to perform fetching the second data and writing the first data atomically.

26. The method of claim 25, further comprising continuing to buffer and service requests to other buffers.

27. The method of claim 25, further comprising:

inserting a read-refresh request periodically into the stream of processor memory requests, wherein the periodic read-refresh requests are sent using refresh addresses that cycle through address bits for a row-address portion and also cycle through bits for a column-address portion;

fetching data as a result of each of the read-refresh requests;

detecting an error in one of the fetched sets of data; and

based on one or more criteria, wherein the criteria include the detecting of the error, performing the bit-swapping operations.

28. The method of claim 27, further comprising varying a value of time between read-refresh requests.

29. The method of claim 27, further comprising varying a priority of the read-refresh requests.

30. The method of claim 27, further comprising inserting an explicit-refresh request periodically into the stream of memory requests to cause memory parts to perform an internally controlled refresh function.

31. The method of claim 27, wherein the method is performed on a single memory card.

32. The method of claim 27, further comprising functionally testing to verify whether, for memory requests having addresses within the range, the one or more bits are swapped, wherein the shifting takes place on a first memory card, and the functionally testing further includes originating test commands and checking results on a second memory card that is substantially identical to the first memory card.

33. The method of claim 19, wherein the detecting of whether the first address is within a specified range of addresses includes comparing the first address to an address specifying an end of the specified range.

34. The method of claim 34, wherein the detecting of whether the first address is within a specified range of addresses further includes comparing the first address to an address specifying an opposite end of the specified range.

35. An information-processing apparatus comprising:

a first memory having a plurality of addressed locations, each location holding a plurality of bits; and

a first control circuit, wherein the first control circuit includes;

a first memory controller coupled to the first memory, the memory controller including;

means for shifting a first subset of bit positions a plurality of bit positions in a first direction for each write-operation address being detected as within the specified range, and for writing the bit-swapped first data to the memory; and

means for reading the first data to the memory, and for shifting a second subset of bit positions a plurality of bit positions in a second direction opposite the first direction for each read-operation address being detected as within the specified range.

36. The apparatus of claim 35, further comprising means for performing an atomic read-write (RMW) operation that includes a first memory request to read from a first address and a second memory request to write to the first address.

37. The apparatus of claim 36, wherein the controller is configured to consider an RMW as one request.

38. The apparatus of claim 36, further comprising means for changing an end address of the specified range between the second and first memory requests, such that data based on the read second data is bit-swapped to produce the first data and written to its same address.

39. The apparatus of claim 38, further comprising means for performing error correction on the read data before bit swapping and writing.

40. The apparatus of claim 36, further comprising:

means for iteratively changing the end address and reading and writing data in a section of the memory in order to dynamically move data in the section of the memory from a normal bit mapping configuration to a bit-swapped mapping configuration.

41. The apparatus of claim 36, further comprising:

means for buffering a first plurality of pending memory requests from a processor;

means for sending a stream of the first processor memory requests from the buffered pending memory requests to the memory; and

means for stopping buffering of processor memory requests in order to perform fetching the second data and writing the first data atomically.

42. The apparatus of claim 36, further comprising:

means for buffering a first plurality of pending memory requests from a processor;

means for sending a stream of the first processor memory requests from the buffered pending memory requests to the memory; and

means for stopping servicing of processor memory requests in order to perform fetching the second data and writing the first data atomically.

43. The apparatus of claim 41, further comprising:

means for inserting a read-refresh request periodically into the stream of processor memory requests, wherein the periodic read-refresh requests are sent using refresh addresses that cycle through address bits for a row-address portion and also cycle through bits for a column-address portion;

means for fetching data as a result of each of the read-refresh requests;

means for detecting an error in one of the fetched sets of data; and

means for, based on one or more criteria that include the detecting of the error, performing the bit-swapping operations.

44. The apparatus of claim 43, further comprising means for varying a value of time between read-refresh requests.

45. The apparatus of claim 43, further comprising means for varying a priority of the read-refresh requests.

46. The apparatus of claim 43, further comprising means for inserting an explicit-refresh request periodically into the stream of memory requests to cause memory parts to perform an internally controlled refresh function.

47. The apparatus of claim 43, wherein the apparatus is implemented on a first memory card.

48. The apparatus of claim 43, further comprising, on a second memory card, means for functionally testing to verify whether, for memory requests having addresses within the range, the one or more bits are swapped, wherein the means for shifting is on the first memory card, and wherein the second memory card is connected to the first memory card.