Memory fence with background lock release

• US 20070067592A1
• Filed: 11/17/2006
• Published: 03/22/2007
• Est. Priority Date: 08/12/2002
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Jeter, Robert
• Granted Patent: US 7,434,016 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

In one embodiment, a processor is operable to issue a first memory request to access a particular memory location, and, prior to completion of the first memory request, to issue a command to release a memory lock on the particular memory location when access to the particular memory location is complete. The processor is further operable to, prior to release of the memory lock, issue a second memory request to access a different memory location. Also a memory management unit is operable to receive the command to release the memory lock and to monitor for when access to the particular memory location is complete. The memory management unit releases the memory lock in response to completion.

Claims

1. An apparatus comprising:

a processor operable to issue a first memory request to access a particular memory location, and, prior to completion of the first memory request, issue a command to release a memory lock on the particular memory location when access to the particular memory location is complete, the processor further operable to, prior to release of the memory lock, issue a second memory request to access a different memory location; and

a memory management unit operable to receive the command to release the memory lock, monitor for when access to the particular memory location is complete, and release the memory lock in response to completion.

2. The apparatus of claim 1 further comprising:

a memory controller operable to return a request identifier (ID) associated with the particular memory location when access to the particular memory location is complete; and

wherein the memory management unit is operable to detect that access is complete by receipt of the request ID.

3. The apparatus of claim 2 wherein the memory management unit is operable to generate the request ID and to include the request ID in the first memory request.

4. The apparatus of claim 2 wherein the memory management unit is operable to construct a condition data structure that associates one or more memory locks with one or more request IDs.

5. The apparatus of claim 4, wherein the memory management unit is operable to, in a background process, compare the request ID returned from the memory controller with the one or more request IDs in the condition data structure.

6. The apparatus of claim 1, wherein the processor is operable to read a sequence of instructions, and, in response to a memory request instruction, to issue the memory request, and, in response to a memory fence instruction, to issue the command to release the memory lock on the particular memory when access to the particular memory location is complete.

7. An method comprising:

issuing a first memory request to access a particular memory location;

issuing, prior to completion of the first memory request, a command to release a memory lock on the particular memory location when access to the particular memory location is complete;

issuing, prior to release of the memory lock, a second memory request to access a different memory location;

monitoring for when access to the particular memory location is complete; and

releasing the memory lock in response to completion.

8. The method of claim 7 further comprising:

returning a request identifier (ID) associated with the particular memory location when access to the particular memory location is complete; and

wherein the step of monitoring includes detecting that access is complete by receipt of the request ID.

9. The apparatus of claim 8 further comprising:

including the request ID in the first memory request.

10. The method of claim 9 further comprising:

constructing a condition data structure that associates one or more memory locks with one or more request IDs.

11. The method of claim 10 further comprising:

comparing, in a background process, the request ID returned from the memory controller with the one ore more request IDs in the condition data structure.

12. The apparatus of claim 11, further comprising:

issuing a memory lock request on the particular memory location.

13. An apparatus comprising:

means for issuing a first memory request to access a particular memory location;

means for issuing, prior to completion of the first memory request, a command to release a memory lock on the particular memory location when access to the particular memory location is complete,

means for issuing, prior to release of the memory lock, a second memory request to access a different memory location;

means for monitoring for when access to the particular memory location is complete; and

means for releasing the memory lock in response to completion.

14. The apparatus of claim 13 further comprising:

means for returning a request identifier (ID) associated with the particular memory location when access to the particular memory location is complete; and

wherein the means for monitoring is operable to detect that access is complete by receipt of the request ID.

15. Software embodied in one or more computer-readable media, comprising:

a memory request instruction that when executed is operable to request access to a particular memory location, and to cause a memory controller to subsequently return a request identifier (ID) associated with the particular memory location when access to the particular memory location is complete; and

a memory fence instruction, the memory fence instruction when executed operable to monitor for return of the request ID associated with the particular memory location and to release a memory lock in response to return of the request ID.

16. The software of claim 15, further comprising:

a memory lock instruction that when executed is operable to request a memory lock on the particular memory location.

17. The software of claim 15, further comprising:

a second memory request instruction that when executed is operable to request access to a different memory location, the second memory request instruction allowed to execute prior to release of the memory lock.

18. The software of claim 15, further comprising:

instruction code that when executed is operable to construct a condition data structure that associates one or more memory locks with one or more request IDs.

19. The software of claim 18, further comprising:

instruction code that when executed is operable to compare returned request IDs with the one or more request IDs in the condition data structure, the comparison being a background process.

20. The software of claim 15, wherein the memory fence instruction includes a synchronize parameter that when executed is operable to prevent execution of instructions subsequent to the memory fence instruction in an instructions sequence, until a time when the memory lock is released.