Processor resource management

• US 20070067611A1
• Filed: 09/22/2006
• Published: 03/22/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W.
• Granted Patent: US 7,725,693 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction group pursuant to a first resource management policy applied to a hardware resource and an execution of the instruction group pursuant to a second resource management policy applied to the hardware resource.

Claims

1-55. -55. (canceled)

56. A device comprising:

a processor having a hardware resource associated with the processor; and

a processor control unit operable to

fetch an instruction to be executed in the processor;

receive a previously selected resource management policy associated with the instruction, the resource management policy having been selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and having been selected from a optimistic resource management policy and a pessimistic resource management policy; and

apply the previously selected resource management policy to the hardware resource.

57. The device of claim 56, wherein the processor control unit further comprises:

a processor control unit operable to enable the processor to execute the instruction.

58. The device of claim 56, wherein the processor control unit further comprises:

a processor control unit operable to

enable the processor to execute the instruction;

fetch another instruction to be executed in the processor;

receive another previously selected resource management policy associated with the another instruction, the another resource management policy having been selected as likely to provide a substantially optimum execution of another instruction group that includes the another instruction, and having been selected from a optimistic resource management policy and a pessimistic resource management policy;

apply the another resource management policy to the hardware resource, and

enable the processor to execute another instruction.

63. The device of claim 56, wherein the processor and the hardware resource are formed on a single chip.

64. The device of claim 56, wherein the processor is formed on a first chip and the hardware resource is formed on a second chip.

65. The device of claim 56, wherein the processor control unit and the processor are formed on a single chip.

66. The device of claim 56, wherein the hardware resource includes a cache.

67. The device of claim 66, wherein the cache includes at least one of an on-chip cache or an off-chip cache.

68. The device of claim 56, wherein the hardware resource includes a branch predictor.

69. The device of claim 56, wherein the hardware resource includes a hardware resource logically associated with the processor.

70. The device of claim 56, wherein the hardware resource includes a hardware resource physically associated with the processor.

71. The device of claim 56, wherein the hardware resource associated with the processor includes a hardware resource managed by the processor.

72. The device of claim 71, wherein the hardware resource managed by the processor includes at least one of a memory, a cache, a bus, a register-file port, and a functional unit.

59. A method comprising:

fetching an instruction to be executed in a central processor unit having an associated resource;

receiving a previously selected resource management policy associated with the instruction, the resource management policy having been selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and having been selected from a optimistic resource management policy and a pessimistic resource management policy;

applying the previously selected resource management policy to the resource; and

executing the instruction in the central processor unit.

60. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource includes fetching an instruction to be executed in a central processor unit having an associated cache resource.

61. The method of claim 60, wherein the associated cache resource includes one of an on-chip cache or an off-chip cache.

62. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource includes fetching an instruction to be executed in a central processor unit having an associated branch predictor resource.

73. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the associated resource including at least one of an associated resource implemented in hardware, software, and/or firmware.

74. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a functional instruction, a branching instruction, a memory instruction, and/or other instruction that may be executed by a processor.

75. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a statement or a portion of a statement.

76. The method of claim 59, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a decoded instruction, a translated instruction, and/or a micro-operation.

77. The method of claim 59, wherein the receiving a previously selected resource management policy associated with the instruction further includes:

fetching a previously selected resource management policy associated with the instruction.

78. A device comprising:

means for fetching an instruction to be executed in a central processor unit having an associated resource;

means for receiving a previously selected resource management policy associated with the instruction, the resource management policy having been selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and having been selected from a optimistic resource management policy and a pessimistic resource management policy;

means for applying the previously selected resource management policy to the resource; and

means for executing the instruction in the central processor unit.