Hierarchical configurations in error-correcting computer systems

• US 20070067673A1
• Filed: 08/18/2006
• Published: 03/22/2007
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Algirdas Avizienis
• Original Assignee: Algirdas Avizienis
• Inventors: Avizienis, Algirdas
• Granted Patent: US 7,861,106 B2
• Time in Patent Office: Days
• US Class Current: 714/12
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and then also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.

Claims

1. Apparatus for correcting errors in a computing system that has plural modules;

said apparatus comprising;

a hierarchical error-correcting system;

at least two receiving connections, for reception by the hierarchical system of error messages from such plural modules of such computing system, respectively; and

at least two sending connections, for return by the hierarchical system of corrective responses to such plural modules of such computing system, respectively.

2. The apparatus of claim 1, in further combination with:

said computing system.

3. The apparatus of claim 1;

wherein;

the hierarchical system comprises at least two first-level caches, each first-level cache holding;

a listing of error messages which respective such modules of such computing system can send via one of the at-least-two receiving connections, and

a listing of respective corrective responses which respective such modules of such computing system can receive via one of the at-least-two sending connections; and

each first-level cache comprises preprogrammed means for responding to receipt of any of the listed error messages from its respective module or modules by returning a respective corrective response.

4. The apparatus of claim 3, in further combination with:

said computing system.

5. The apparatus of claim 3;

wherein the hierarchical system further comprises;

at least one second-level cache having;

at least two receiving connections for receiving error messages from said at least two first-level caches, respectively, and

at least two sending connections for returning corrective responses to said at least two first-level caches, respectively.

6. The apparatus of claim 5:

wherein the at least one second-level cache comprises at least two second-level caches; and

further comprising at least one third-level cache having;

at least two receiving connections for receiving error messages from said at least two second-level caches, respectively, and

at least two sending connections for returning corrective responses to said at least two second-level caches, respectively.

7. The apparatus of claim 6, further comprising:

at least one bottom-level cache that is supported by a hypothalamus having preprogrammed means for controlling interruption and restoration of power to the at least one bottom-level cache that is at an immediately higher level of the hierarchy.

8. The apparatus of claim 7, further comprising:

at least one relatively higher-level cache, at a level above said bottom-level cache, that is supported by another hypothalamus having preprogrammed means for controlling interruption and restoration of power to the at least one relatively higher-level cache;

whereby the relatively higher-level cache can continue in operation if the hypothalamus that supports the bottom-level cache fails.

9. The apparatus of claim 7, in further combination with:

said computing system.

10. The apparatus of claim 7, further comprising:

at further levels intermediate between the at least one third-level cache and the at least one bottom-level cache, one or more further caches that are nested in substantially the same way as the first-, second- and third-level caches.

11. The apparatus of claim 5, for use if such plural computing-system modules comprise at least two diverse processors or programs, or both, for generating parallel candidate results from generally parallel computations in the at least two diverse processors or programs, respectively;

said apparatus further comprising;

at least one conflict-resolver module that compares such parallel results and eliminates one or more of such results.

12. The apparatus of claim 11, wherein:

at least one of the caches includes in its respective listing a corrective message that removes power from such computing-system module, or from a higher-level cache, whose results are eliminated.

13. The apparatus of claim 11, wherein:

at least one of the caches includes in its respective listing a corrective message that inserts, powers up and provides initial data for a spare unit in place of such computing-system module, or from a higher-level cache, whose results are eliminated.

14. The apparatus of claim 1, for use if such plural computing-system modules comprise at least two diverse processors or programs, or both, for generating parallel candidate results from generally parallel computations in the at least two diverse processors or programs, respectively;

said apparatus further comprising;

at least one conflict-resolver module that compares such parallel results and eliminates one or more of such results.

15. The apparatus of claim 14, wherein at least one of the caches includes in its respective listing:

a corrective message that removes power from such computing-system module, or from a higher-level cache, whose results are eliminated; and

a corrective message that inserts, powers up and provides initial data for a spare unit in place of such computing-system module, or a higher-level cache, whose results are eliminated.

16. The apparatus of claim 1, wherein:

at least the error-correcting system is in the form of a System on Chip (SoC).

17. A method of controlling errors in a computing system that has multiple modules in a hierarchical configuration;

said method comprising the steps of;

providing a hierarchical error-controlling system having a configuration that very generally parallels the hierarchical configuration of the computing system;

providing a multiplicity of interconnections between elements of the computing system and corresponding elements of the very generally parallel error-controlling system, respectively; and

in event of errors by elements of the computing system;

passing error messages from the computing-system elements to the corresponding error-controlling-system elements, by way of the interconnections, and

returning corrective messages from the error-controlling-system elements to the computing-system elements, by way of the interconnections.

18. Apparatus for correcting errors in a computing system that has plural modules that comprise at least two diverse processors or programs, or both, for generating parallel candidate results from generally parallel computations in the at least two diverse processors or programs, respectively;

said apparatus comprising;

a hierarchical error-correcting system;

at least two receiving connections, for reception by the hierarchical system of error messages from the modules of the computing system, respectively; and

at least two sending connections, for return by the hierarchical system of corrective responses to the modules of the computing system, respectively;

wherein the hierarchical system comprises at least two first-level caches, each first-level cache holding;

a listing of error messages which the respective modules of the computing system can send via one of the at-least-two connections, and

a listing of respective corrective responses which the respective modules of the computing system can receive via the second of the at-least-two connections;

wherein each first-level cache comprises preprogrammed means for responding to receipt of any of the listed error messages from its respective module or modules by returning a respective corrective response; and

wherein the hierarchical system further comprises at least two second-level caches, each having;

at least two receiving connections for receiving error messages from said at least two first-level caches, respectively, and

at least two sending connections for returning corrective responses to said at least two first-level caches, respectively; and

further comprising at least one third-level cache having;

at least two receiving connections for receiving error messages from said at least two second-level caches, respectively, and

at least two sending connections for returning corrective responses to said at least two second-level caches, respectively;

further comprising at least one bottom-level cache that is supported by a hypothalamus having preprogrammed means for controlling interruption and restoration of power to the at least one bottom-level cache that is at an immediately higher level of the hierarchy;

further comprising, at further levels intermediate between the at least one third-level cache and the at least one bottom-level cache, one or more further caches that are nested in substantially the same way as the first-, second- and third-level caches; and

further comprising at least one conflict-resolver module that compares the parallel results and eliminates one or more of the results; and

wherein at least one of the first-level caches includes in its respective listing a corrective message that removes power from the computing-system module whose results are eliminated.

19. The apparatus of claim 18, in further combination with:

said computing system.

20. The apparatus of claim 19, wherein:

at least the error-correcting system is in the form of a System on Chip (SoC).