Testing apparatus and testing method

• US 20070067685A1
• Filed: 09/01/2006
• Published: 03/22/2007
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Sato, Kazuhiko, Yamada, Masuhiro, Ohsawa, Toshimi
• Granted Patent: US 7,441,166 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.

Claims

1. A testing apparatus that concurrently tests a plurality of memories under test, comprising:

a pattern generator that generates an address signal and a data signal to be supplied to the plurality of memories under test and an expectation signal to be output from the memory under test according to the address signal and the data signal;

a plurality of logic comparators that are provided corresponding to each of the plurality of memories under test and compare an output signal output from the plurality of memories under test according to the address signal and the data signal and the expectation signal to generate fail data when the output signal and the expectation signal are not identical with each other;

a plurality of fail memories that are provided corresponding to each of the plurality of memories under test and store the fail data generated from the plurality of logic comparators in association with an address shown by the address signal;

a plurality of memory controllers that are provided corresponding to each of the plurality of memories under test and generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories;

a plurality of universal buffer memories that are provided corresponding to each of the plurality of memories under test and store the bad address information generated from the plurality of memory controllers; and

a plurality of bad information writing sections that are provided corresponding to each of the plurality of memories under test and concurrently write a first bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.

2. The testing apparatus as claimed in claim 1, further comprising:

a plurality of first buses that respectively connect the plurality of fail memories to the plurality of memory controllers; and

a plurality of second buses that respectively connect the plurality of memory controllers to the plurality of universal buffer memories.

3. The testing apparatus as claimed in claim 1, wherein the memory controller generates the bad address information with a format peculiar to the memory under test and supplies the generated information to the universal buffer memory.

4. The testing apparatus as claimed in claim 3, wherein the memory controller operates based on a program loaded according to a type of the memory under test in order to generate the bad address information with the format peculiar to the memory under test.

5. The testing apparatus as claimed in claim 1, wherein

the memory under test comprises a plurality of block areas respectively having a plurality of page areas respectively including a main area storing data and an extended area storing the first bad information,

the fail memory stores the fail data on each of the block areas in the memory under test,

the memory controller generates the bad address information showing a block address of the bad block area in the memory under test with reference to the fail memory,

the universal buffer memory stores the bad address information generated from the memory controller, and

the bad information writing section writes the first bad information into the extended area in the block area shown by the bad address information stored on the universal buffer memory.

6. The testing apparatus as claimed in claim 5, wherein

the pattern generator generates a page address signal showing the page area to supply the generated signal to the plurality of bad information writing sections, and

the plurality of bad information writing sections write the first bad information into the extended area in the page area shown by the page address signal generated from the pattern generator, the page area being included in the block area shown by the bad address information stored on the plurality of universal buffer memories provided corresponding to each of the plurality of memories under test.

7. The testing apparatus as claimed in claim 1, wherein

the memory controller comprises:

a data reading section that reads data stored on a predetermined address of the fail memory;

a fail judging section that judges whether the fail data are included in the data read from the data reading section or not; and

a bad address information generating section that generates the bad address information when the fail judging section judges that the fail data are included in the data read from the data reading section.

8. The testing apparatus as claimed in claim 1, wherein

the plurality of memory controllers generate a second bad information with a format peculiar to the memory under test based on the fail data stored on the plurality of fail memories,

the plurality of universal buffer memories store the second bad information generated from the plurality of memory controllers, and

the plurality of bad information writing sections write the second bad information stored on the plurality of universal buffer memories into the plurality of memories under test.

9. The testing apparatus as claimed in claim 8, wherein the memory controller operates based on a program loaded according to a type of the memory under test in order to generate the second bad information with the format peculiar to the memory under test.

10. The testing apparatus as claimed in claim 8, further comprising:

a plurality of first fail information memories that are provided corresponding to each of the plurality of memories under test and store the second bad information generated from the plurality of memory controllers;

a plurality of second fail information memories that are provided corresponding to each of the plurality of memories under test and store the second bad information read from the plurality of memories under test; and

a quality deciding section that compares the second bad information stored on the first fail information memory and the second bad information stored on the second fail information memory to decide the good or bad of the plurality of memories under test.

11. The testing apparatus as claimed in claim 10, further comprising:

a plurality of first buses that respectively connect the plurality of fail memories and the plurality of first fail information memories to the plurality of memory controllers; and

a plurality of second buses that respectively connect the plurality of memory controllers to the plurality of universal buffer memories.

12. The testing apparatus as claimed in claim 11, wherein

the memory under test comprises a plurality of main areas storing data and a special area storing the second bad information, and

the bad information writing section writes the second bad information into the special area included in the memory under test.

13. A testing apparatus that concurrently tests a plurality of memories under test, comprising:

a pattern generator that generates an address signal and a data signal to be supplied to the plurality of memories under test and an expectation signal to be output from the memory under test according to the address signal and the data signal;

a plurality of logic comparators that are provided corresponding to each of the plurality of memories under test and compare an output signal output from the plurality of memories under test according to the address signal and the data signal and the expectation signal to generate fail data when the output signal and the expectation signal are not identical with each other;

a plurality of fail memories that are provided corresponding to each of the plurality of memories under test and store the fail data generated from the plurality of logic comparators in association with an address shown by the address signal;

a plurality of memory controllers that are provided corresponding to each of the plurality of memories under test and generate bad information with a format peculiar to the memory under test based on the fail data stored on the plurality of fail memories;

a plurality of universal buffer memories that are provided corresponding to each of the plurality of memories under test and store the bad information generated from the plurality of memory controllers; and

a plurality of bad information writing sections that are provided corresponding to each of the plurality of memories under test and write the bad information stored on the plurality of universal buffer memories into the plurality of memories under test.

14. A testing method for concurrently testing a plurality of memories under test, comprising:

generating an address signal and a data signal to be supplied to the plurality of memories under test and an expectation signal to be output from the memory under test according to the address signal and the data signal;

comparing an output signal output from the plurality of memories under test according to the address signal and the data signal and the expectation signal to generate fail data when the output signal and the expectation signal are not identical with each other by means of a plurality of logic comparators provided corresponding to each of the plurality of memories under test;

storing the fail data in association with an address shown by the address signal on a plurality of fail memories provided corresponding to each of the plurality of memories under test;

generating bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories by means of a plurality of memory controllers provided corresponding to each of the plurality of memories under test;

storing the bad address information generated from the plurality of memory controllers on a plurality of universal buffer memories provided corresponding to each of the plurality of memories under test; and

concurrently writing a first bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories by means of a plurality of bad information writing sections provided corresponding to each of the plurality of memories under test.

15. A testing method for concurrently testing a plurality of memories under test, comprising:

generating an address signal and a data signal to be supplied to the plurality of memories under test and an expectation signal to be output from the memory under test according to the address signal and the data signal;

comparing an output signal output from the plurality of memories under test according to the address signal and the data signal and the expectation signal to generate fail data when the output signal and the expectation signal are not identical with each other by means of a plurality of logic comparators provided corresponding to each of the plurality of memories under test;

storing the fail data generated from the plurality of logic comparators in association with an address shown by the address signal by means of a plurality of fail memories provided corresponding to each of the plurality of memories under test;

generating bad information with a format peculiar to the memory under test based on the fail data stored on the plurality of fail memories by means of a plurality of memory controllers provided corresponding to each of the plurality of memories under test;

storing the bad information generated from the plurality of memory controllers by means of a plurality of universal buffer memories provided corresponding to each of the plurality of memories under test; and

writing the bad information stored on the plurality of universal buffer memories into the plurality of memories under test by means of a plurality of bad information writing sections provided corresponding to each of the plurality of memories under test.