Integrated Circuit Testing Module Configured for Set-up and Hold Time Testing

• US 20070067687A1
• Filed: 10/25/2006
• Published: 03/22/2007
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Inapac Technology Incorporated (Rambus Inc.)
• Inventors: Ong, Adrian
• Granted Patent: US 8,166,361 B2
• Time in Patent Office: Days
• US Class Current: 714/731
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

Claims

1. A system comprising:

a clock synchronization component;

one or more input components configured to receive signals from an automated testing equipment configured to test an integrated circuit;

one or more data generating components configured to generate test signals responsive to the signals received from the automated testing equipment;

a clock adjustment component configured to adjust synchronization between the clock adjustment component and one or more elements of the generated test signals to be conveyed to the integrated circuit; and

one or more output components configured to convey the generated test signals to the integrated circuit, the integrated circuit being separable from the one or more output components.

2. The system of claim 1, further including a command generating component configured to control timing of commands to be sent to the integrated circuit.

3. The system of claim 1, further including an address generating component configured to generate addresses to be sent to the integrated circuit.

4. The system of claim 1, further including the integrated circuit.

5. The system of claim 1, wherein the one or more data generating components include a test plan memory component configured to store test plans for testing set-up time or hold time.

6. The system of claim 1, wherein the one or more input components are configured to receive the signals from the automated testing equipment at a first clock frequency, and the one or more output components are configured to convey the generated test signals to the integrated circuit at a second clock frequency higher than the first clock frequency.

7. The system of claim 1, wherein the one or more input components are configured to receive the signals from the automated testing equipment a first slew rate, and the one or more data generating components are configured to convey the generated signals to the integrated circuit at a second slew rate faster than the first slew rate.

8. A method comprising:

attaching an automated testing equipment to a test module having a clock adjustment component configured to determine a clock synchronization between a clock signal sent to an integrated circuit and a clock signal used to determine when to expect data from the integrated circuit;

attaching the integrated circuit to be tested to the test module;

receiving signals from the automated testing equipment at the test module;

testing the integrated circuit according to the steps of;

(a) generating an adjustment to the clock synchronization responsive to the signals received from the automated testing equipment,

(b) conveying test signals to the integrated circuit using the adjustment to the clock synchronization,

(c) receiving data from the integrated circuit responsive to the conveyed test signals, and

(d) comparing the received data to an expected result.

9. The method of claim 8, further comprising repeating steps (a), (b), (c), and (d), using a different adjustment to the clock synchronization.

10. The method of claim 9, wherein the test module is configured to test a minimum set-up time.

11. The method of claim 9, wherein the test module is configured to test a minimum hold time.

12. The test method of claim 9, further comprising generating the test signals within the test module responsive to the signals received from the automated testing equipment.

13. The method of claim 12, wherein the test signals include at least one command.

14. The method of claim 12, wherein the data include at least one address.

15. The method of claim 8, wherein the adjustment to the clock synchronization is configured to test the hold time of the integrated circuit.

16. The method of claim 8, wherein the signals received from the automated testing equipment are received a first slew rate, and the generated test signals are conveyed to the integrated circuit at a second slew rate faster than the first slew rate.

17. The method of claim 8, wherein the signals received from the automated testing equipment are received a first clock frequency, and the generated test signals are conveyed to the integrated circuit at a second clock frequency higher than the first clock frequency.

18. An integrated circuit tested according to the method of claim 8.

19. A system comprising:

means for coupling a test module between an automated testing equipment and an integrated circuit to be tested;

means for configuring the test module for testing of the integrated circuit;

means for receiving signals from the automated testing equipment at the test module; and

means for testing a slew rate, minimum set-up time, or minimum hold time of the integrated circuit.