Substrate noise tool

• US 20070067747A1
• Filed: 04/07/2006
• Published: 03/22/2007
• Est. Priority Date: 09/19/2005
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Checka, Nisha, Chandrakasan, Anantha, Reif, Rafael
• Granted Patent: US 7,480,879 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

Claims

1. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said circuit comprises a plurality of standard cells, comprising:

creating a noise macrocell for each of said standard cells;

simulating said integrated circuit to generate an event model;

creating a model of said substrate; and

simulating said integrated substrate model and said noise model using said event model to create a profile of said substrate noise.

2. The method of claim 1, wherein said integrated circuit comprises at least one power line, one ground line, and one interconnect, wherein said noise macrocell is created comprising components selected from the group consisting of current sources representing noise in said power line, current sources representing noise in said ground line, current sources representing noise injected into said substrate, the impedance between said substrate and said ground line, the impedance between said substrate and said power line, the local impedance between said power line and said ground line, and the impedance between said interconnect and said substrate.

3. The method of claim 1, wherein said substrate model is generated using a commercially available tool.

4. The method of claim 1, wherein said substrate model is created comprising the steps of:

receiving from a user an estimated die size and a substrate resistivity;

dividing said die size into equal sized partitions;

assuming equal distribution of substrate contacts between said partitions;

calculating the resistance between each pair of partitions based on the distance between said pair and said inputted resistivity; and

creating a resistive mesh network using said calculated resistances.

5. The method of claim 1, wherein said substrate model is created comprising the steps of:

inputting a circuit layout and the substrate resistivity;

determining the location of each substrate contact based on said layout;

calculating the resistance between each pair of substrate contacts based on the distance between said pair and said inputted resistivity; and

creating a resistive mesh network using said calculated values.

6. The method of claim 2, further comprising the step of creating a library of characterized noise macrocells, wherein said characterization comprises the steps of:

simulating each of said current sources using a plurality of different input rise times; and

simulating each of said current sources using a plurality of different output load capacitances.

7. A software program for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said circuit comprises a plurality of standard cells, comprising:

a computer readable medium;

means for creating a noise macrocell for each of said standard cells;

means for simulating said integrated circuit to generate an event model;

means for creating a model of said substrate; and

means for simulating said integrated substrate model and said noise model using said event model to create a profile of said substrate noise.

8. The software program of claim 7, wherein said integrated circuit comprises at least one power line, one ground line, and one interconnect, wherein said noise macrocell is created comprising components selected from the group consisting of current sources representing noise in said power line, current sources representing noise in said ground line, current sources representing noise injected into said substrate, the impedance between said substrate and said ground line, the impedance between said substrate and said power line, the local impedance between said power line and said ground line, and the impedance between said interconnect and said substrate.

9. The software program of claim 7, wherein said means for creating said substrate model comprises a commercially available tool.

10. The software program of claim 7, wherein said means for creating said substrate model comprises:

means for receiving from a user an estimated die size and a substrate resistivity;

means for dividing said die size into equal sized partitions;

means for assuming equal distribution of substrate contacts between said partitions;

means for calculating the resistance between each pair of partitions based on the distance between said pair and said inputted resistivity; and

means for creating a resistive mesh network using said calculated resistances.

11. The software program of claim 7, wherein said means for creating said substrate model comprises:

means for inputting a circuit layout and the substrate resistivity;

means for determining the location of each substrate contact based on said layout;

means for calculating the resistance between each pair of substrate contacts based on the distance between said pair and said inputted resistivity; and

means for creating a resistive mesh network using said calculated values.

12. The software program of claim 7, further comprising means for creating a library of characterized noise macrocells, wherein said means for characterization comprises:

means for simulating each of said current sources using a plurality of different input rise times; and

means for simulating each of said current sources using a plurality of different output load capacitances.

13. A method for analyzing the substrate noise of an integrated circuit, wherein said integrated circuit comprises at least one power line, one ground line, and one interconnect, wherein said circuit comprises a plurality of standard cells, comprising:

creating a noise macrocell for each of said standard cells;

wherein said noise macrocell comprises a current source representing noise in said power line, a current source representing noise in said ground line, a current source representing noise injected into said substrate, an impedance between said substrate and said ground line, an impedance between said substrate and said power line, an local impedance between said power line and said ground line, and an impedance between said interconnect and said substrate.

14. The method of claim 13, further comprising the step of creating a library of characterized noise macrocells, wherein said characterization comprises the steps of:

simulating each of said current sources using a plurality of different input rise times; and

simulating each of said current sources using a plurality of different output load capacitances.

15. The method of claim 13, wherein said standard cells comprise switching elements having a known geometry, wherein said impedance between said substrate and said ground line of each standard cell is computed based on the geometry of said switching elements within said standard cell.

16. The method of claim 13, wherein said standard cells comprise switching elements having a known geometry, wherein said impedance between said substrate and said power line of each standard cell is computed based on the geometry of said switching elements within said standard cell.

17. The method of claim 13, wherein said local impedance between said power line and said ground line is determined by performing an AC simulation of said standard cell.

18. The method of claim 13, wherein said impedance between said interconnect and said substrate is determined using an eternal parastic extraction tool.