Substrate noise tool
First Claim
1. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said circuit comprises a plurality of standard cells, comprising:
- creating a noise macrocell for each of said standard cells;
simulating said integrated circuit to generate an event model;
creating a model of said substrate; and
simulating said integrated substrate model and said noise model using said event model to create a profile of said substrate noise.
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Abstract
System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.
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Citations
18 Claims
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1. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said circuit comprises a plurality of standard cells, comprising:
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creating a noise macrocell for each of said standard cells;
simulating said integrated circuit to generate an event model;
creating a model of said substrate; and
simulating said integrated substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A software program for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said circuit comprises a plurality of standard cells, comprising:
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a computer readable medium;
means for creating a noise macrocell for each of said standard cells;
means for simulating said integrated circuit to generate an event model;
means for creating a model of said substrate; and
means for simulating said integrated substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for analyzing the substrate noise of an integrated circuit, wherein said integrated circuit comprises at least one power line, one ground line, and one interconnect, wherein said circuit comprises a plurality of standard cells, comprising:
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creating a noise macrocell for each of said standard cells;
wherein said noise macrocell comprises a current source representing noise in said power line, a current source representing noise in said ground line, a current source representing noise injected into said substrate, an impedance between said substrate and said ground line, an impedance between said substrate and said power line, an local impedance between said power line and said ground line, and an impedance between said interconnect and said substrate. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification