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Method and system for enhancing circuit design process

  • US 20070067748A1
  • Filed: 09/22/2005
  • Published: 03/22/2007
  • Est. Priority Date: 09/22/2005
  • Status: Active Grant
First Claim
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1. A method for designing an integrated circuit, comprising:

  • a) inserting wire model objects (“

    WMOs”

    ) into the schematic of said circuit based on sizing and placement of components of said circuit;

    b) performing an early timing analysis (“

    ETA”

    ) on said schematic; and

    c) repeating steps a) and b) after re-sizing and/or re-placing said components if said ETA fails.

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