Method and system for enhancing circuit design process

• US 20070067748A1
• Filed: 09/22/2005
• Published: 03/22/2007
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Heymann, Omer, Leibowitz, Moshe, Noy, Gil, Goren, Lidor, Amit, Niv, Speiser, Maya, Bustin, Ronit, Raphayevich, Alex
• Granted Patent: US 7,331,029 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Claims

1. A method for designing an integrated circuit, comprising:

a) inserting wire model objects (“

WMOs”

) into the schematic of said circuit based on sizing and placement of components of said circuit;

b) performing an early timing analysis (“

ETA”

) on said schematic; and

c) repeating steps a) and b) after re-sizing and/or re-placing said components if said ETA fails.

2. A method according to claim 1, wherein inserting comprises deriving a second schematic file from a first schematic file relating to the logical connections in the circuit and to physical size of components of said circuit, and from a placement data relating to physical locations of said components, and inserting the wire model objects into said second schematic file by:

a) estimating a wiring routing geometry for each signal path in said circuit;

b) selecting one or more cascading wire model objects (“

WMOs”

) for each segment in each geometry; and

c) substituting each signal path with the respective one or more WMOs;

3. A method according to claim 1, wherein the wire model objects are inserted according to optimized wires'"'"' routing geometries.

4. A method according to claim 3, wherein the optimized wires routing geometries are generated by employing computational geometry algorithms to calculate optimized estimations for the anticipated interconnection routing geometries according to the placement data.

5. A method according to claim 4, wherein optimized estimations are calculated in respect of a “

Rectilinear Steiner Tree”

like algorithm.

6. A method according to claim 1, wherein the wire model objects are selected from a library of wire model objects, wherein the selection is based on a predefined set of selection rules.

7. A method according to claim 1, further comprising:

(i) completing the layout of the circuit by incorporating routing into it, based on the most recently updated first schematic file and placement data, (ii) validating the completed layout, and (iii) if the final timing analysis fails, updating the first schematic file and, if required, modifying said placement data accordingly, and repeating steps (i) and (ii) until passing final timing analysis, to obtain final timing closure for said circuit.

8. A computer program product for designing an integrated circuit, wherein said computer program product comprises a computer useable medium that includes a computer readable program, said computer readable program, when executed on a computer, causes said computer to:

a) insert wire model objects (“

WMOs”

) into the schematic of said circuit based on sizing and placement of components of said circuit;

b) perform an early timing analysis (“

ETA”

) on said schematic; and

c) to repeat steps a) and b) after re-sizing and/or re-placing said components if said ETA fails.

9. A computer program product according to claim 8, wherein the inserting wire model objects (“

WMOs”

) comprises deriving a second schematic file from a first schematic file relating to the logical connections in the circuit and to physical size of components of said circuit, and from a placement data relating to physical locations of said components by;

a) estimating a wiring routing geometry for each signal path in said circuit;

b) selecting one or more cascading wire model objects (“

WMOs”

) for each segment in each geometry; and

c) substituting each signal path with the respective one or more WMOs;

wherein the early timing analysis (“

ETA”

) is performed on said second schematic file; and

wherein said first schematic file is re-generated or updated according to the re-sizing and/or re-placing of the components.

10. A computer program product according to claim 9, wherein the wire model objects are inserted according to optimized wires'"'"' routing geometries.

11. A computer program product according to claim 10, wherein the optimized wires'"'"' routing geometries are generated by employing computational geometry algorithms to calculate optimized estimations for the anticipated interconnection routing geometries according to the placement data.

12. A computer program product according to claim 11, wherein optimized estimations are calculated in respect of a “

Rectilinear Steiner Tree”

like algorithm.

13. A computer program product according to claim 9, wherein the wire model objects are selected from a library of wire model objects, wherein the selection is based on a predefined set of selection rules.

14. A system for designing an integrated circuit, comprising:

a) a wire model objects generator (“

WMG”

) for generating and inserting wire model objects (“

WMOs”

) into the schematic of said circuit based on sizing and placement of components of said circuit;

b) an early timing analyzer for performing an early timing analysis (“

ETA”

) on said schematic; and

c) a central processor for causing said generator to generate and insert said WMOs, and for generating and inserting new WMOs after re-sizing and/or re-placing said components, if said ETA fails.

15. A system according to claim 14, wherein the wire model generator (“

WMG”

) retrieves connectivity and placement data from a first schematic file associated with the circuit to generate a second schematic file in which the wire model objects (“

WMOs”

) substitute every signal path in said circuit.

16. A system according to claim 14, wherein the wire model generator (“

WMG”

) comprises;

a) a connectivity and placement data extractor for retrieving from the first schematic file the connectivity and placement data;

b) a geometry estimator (“

GE”

) for utilizing the retrieved connectivity and placement data to estimate a corresponding wiring routing geometry for each signal in the circuit, said geometry may consist of one or more source and target points interconnected by line segments.

a wire model embedder (“

WME”

) for deciding the number and type of WMOs each segment and “

via”

connection will be substituted with; and

c) an insertion means for generating the second schematic file by inserting the WMOs into the circuit schematic, said insertion means may decide to add intermediate nodes to the second schematic file to accommodate for cascading WMOs.

17. A system according to claim 16, wherein the general estimator (“

GE”

) estimates the routing geometry using a Rectilinear Steiner Tree like algorithm.