Method and system for embedding wire model objects in a circuit schematic design

• US 20070067749A1
• Filed: 09/22/2005
• Published: 03/22/2007
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Heymann, Omer, Leibowitz, Moshe, Noy, Gil, Goren, Lidor, Amit, Niv, Speiser, Maya, Bustin, Ronit, Raphayevich, Alex
• Granted Patent: US 7,290,235 B2
• Time in Patent Office: Days
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Claims

1. A method for schematically embedding wire model objects into a schematic design of an integrated circuit, comprising:

a) estimating a wiring routing geometry for each signal path in said circuit;

b) selecting one or more cascading wire model objects (“

WMOs”

) for each segment in each geometry; and

c) substituting each signal path with the respective one or more WMOs.

2. A method according to claim 1, wherein substituting comprises insertion of wire model objects (“

WMOs”

) by associating each signal name in the circuit to its estimated wiring routing geometry and selecting for each segment in each geometry one or more cascading WMOs to be associatively coupled to one another and to the source and target points of the respective signal name.

3. A method according to claim 2, further comprising deriving a second schematic file from the schematic file relating to the logical connections in the circuit and to physical size of components of said circuit, and from a placement data relating to physical locations of said components, in which wire model objects substitute the signal paths.

4. A method according to claim 2, wherein the association is made using connection labels, wherein input/output (“

I/O”

) terminals in the circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said terminals.

5. A method according to claim 3, wherein the second schematic design file is displayable on a computer display.

6. A method according to claim 5, wherein each signal path of interest in the second schematic design is traceable by navigating from one circuit'"'"'s node to another by using, ‘

clicking’

or touching, displayed connection labels associated with said signal path.

7. A method according to claim 6, wherein discrete elements of the WMOs associated with the signal path of interest are displayable.

8. A method according to claim 6, wherein the WMOs associated with the signal path of interest are displayable as symbols.

9. A method according to claim 1, wherein the known estimated wiring routing further comprises “

via”

connections, and a corresponding WMO is selected for each of said “

via”

connections.

10. A computer program product for schematically embedding wire model objects into a schematic design of an integrated circuit, comprising a computer useable medium that includes a computer readable program;

said computer readable program, when executed on a computer, may cause said computer to;

estimate a wiring routing geometry for each signal path in said circuit;

select one or more cascading wire model objects (“

WMOs”

) for each segment in each geometry and to substitute each signal path with the respective one or more WMOs.

11. A computer program product according to claim 10, wherein substitute comprises insertion of the wire model objects (“

WMOs”

) by associating each signal name in the circuit to its estimated wiring routing geometry and selecting for the segment(s) of each geometry one or more WMO to be associatively coupled to one another and to the source and target points of the respective signal name.

12. A computer program product according to claim 11, wherein the association is made using connection labels, wherein input/output (“

I/O”

) terminals in the full custom circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said terminals.

13. A computer program product according to claim 10, further comprising deriving a second schematic file from the schematic file relating to the logical connections in the circuit and to physical size of components of said circuit, and from a placement data relating to physical locations of said components, in which wire model objects substitute the signal paths.

14. A system for schematically embedding wire model objects into a schematic design of an integrated circuit, comprising:

a wire model embedder (“

WME”

) for estimating a wiring routing geometry for each signal path in said circuit;

selecting one or more cascading wire model objects (“

WMOs”

) for each segment in each geometry; and

for substituting each signal path with the respective one or more WMOs.

15. A system according to claim 14, wherein the wire model embedder (“

WME”

) derives from the schematic design file of the circuit a second schematic design file by inserting one or more wire model objects (“

WMOs”

) between components of said circuit by;

associating each signal name in the circuit to its estimated wiring routing geometry; and

selecting for the segment(s) of said geometry one or more WMO, wherein said WMOs are associatively coupled to one another and to source and target points of the respective signal name using common labels.

16. A system according to claim 14, further comprising an input memory for storing therein, inter alia, the first schematic design file, the content of which may contain data relating to the physical geometry of wiring routing of essentially every signal path in the circuit, and to the original logical connectivity within the circuit, said geometry being definable by a cluster consisting of one or more source and target points, and by line segments that interconnect these points.

17. A system according to claim 14, wherein the wire model embedder (“

WME”

) comprises;

a wire model renderer (“

WMR”

) for estimating the wire routing geometries;

a model decision maker (“

MDM”

) for selecting the WMOs each segment should be substituted with; and

a new connectivity generator (“

NCG”

) for substituting the signal paths with the respective WMOs, whereby to derive the second schematic design file.

18. A system according to claim 17, further comprising an output memory for storing therein the resulting second schematic file.

19. A system according to claim 17, wherein the association is made using connection labels, wherein input/output (“

I/O”

) terminals in the full custom circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said terminals.

20. A system according to claim 23, wherein the estimated wiring routing further comprises “

via”

connections, and a corresponding WMO is selected for each of said “

via”

connections.