Solid-state image pickup device

• US 20070069248A1
• Filed: 07/25/2006
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ohta, Sougo
• Application Number:
  US11/491,933
• Publication Number:
  US 20070069248A1
• Time in Patent Office: Days
• US Class Current: 257/239
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Provided is a solid-state image pickup device which comprises well contacts and well wirings for supplying a reference voltage to a well and can suppress a reduction in an amount of light received even when a pixel area is decreased. As a well wiring, used is a well main-wiring 4 which is formed in a same process as that in which gates of respective transistors are formed, using a same material as that of the gates of respective transistors. In a pixel region (PXR), the well wiring and the well contact comprises the well main-wiring 4, a well sub-wiring 6 in a first wiring layer 10 immediately above the well main-wiring 4, contacts 3 and 5 provided in a gate electrode layer 9. The well wiring and the well contact are not formed in wiring layers above a second wiring layer 11.

Claims

1. A solid-state image pickup device including a pixel region and a peripheral circuitry region on a semiconductor substrate having a well region of a first conductivity type, comprising:

a plurality of photodiodes of a second conductivity type, which are provided in the well region;

a plurality of floating diffusions of the second conductivity type, which are provided in the well region;

a plurality of transfer gates provided for each of the photodiodes on the semiconductor substrate; and

a plurality of well main-wirings formed on a same layer as that on which the transfer gates are formed, wherein

a reference voltage is supplied via the well main-wirings from the peripheral circuitry region to the well region within the pixel region.

2. The solid-state image pickup device according to claim 1, wherein the pixel region further comprises:

a plurality of well sub-wirings provided in a lowermost layer among a plurality of metal wiring layers;

a plurality of first contacts for connecting the well main-wirings and the well sub-wirings; and

a plurality of second contacts for connecting the well sub-wirings and the well region.

3. The solid-state image pickup device according to claim 2, wherein the well region having the first contacts connected thereto further comprises a doped region of the first conductivity type.

4. The solid-state image pickup device according to claim 2, wherein the peripheral circuitry region further comprises a plurality of third contacts for connecting the well main-wirings and the well region.

5. The solid-state image pickup device according to claim 2, wirings provided in an uppermost layer among the plurality of the metal wiring layers are connected to the well main-wirings only in the peripheral circuitry region.

6. The solid-state image pickup device according to claim 1, wherein each of the well main-wirings is provided for each n rows, where n is an even number.

7. The solid-state image pickup device according to claim 6, further comprising

a plurality of reset transistors, each of which is shared by a combination of n pixels adjacent in a column direction, wherein

the well main-wirings extend on an edge of the combination of the pixels in a column direction.

8. The solid-state image pickup device according to claim 7, wherein each of the plurality of second contacts is provided on a first or nth pixel of n pixels adjacent in a column direction.