Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit
First Claim
1. A single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor and a first n-channel MOS transistor, which are formed on a substrate having an SOI structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein:
- each of said first p-channel MOS transistor and said first n-channel MOS transistor is combined with a second MOS transistor having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together, so as to formed a double structure.
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Accused Products
Abstract
Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).
15 Citations
13 Claims
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1. A single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor and a first n-channel MOS transistor, which are formed on a substrate having an SOI structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein:
each of said first p-channel MOS transistor and said first n-channel MOS transistor is combined with a second MOS transistor having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together, so as to formed a double structure. - View Dependent Claims (3, 4, 5)
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2. A single-event-effect tolerant SOI-based inverter comprising:
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a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor and a second n-channel MOS transistor, which are formed on a substrate having an SOI structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein;
said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistor are arranged to form an inverter circuit;
respective gates of said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistors are connected to a common node so as to be connected to an input of said inverter circuit, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistor are connected together, whereby said first and second p-channel MOS transistors are formed as a double-structured p-channel MOS transistor, and said first and second n-channel MOS transistors are formed as a double-structured n-channel MOS transistor.
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6. A single-event-effect tolerant SOI-based 2-input NAND element comprising:
- a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in parallel with each other; and
a pair of a first n-channel MOS transistor and a second n-channel MOS transistor which have channels connected in series with each other, wherein;
said p-channel MOS transistor pair and said n-channel MOS transistor pair are formed on a substrate having an SOI structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;
respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;
respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input; and
a node between said p-channel MOS transistor pair and said n-channel MOS transistor pair is connected to an output, wherein each of said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure. - View Dependent Claims (7)
- a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in parallel with each other; and
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8. A single-event-effect tolerant SOI-based 3-input NAND element comprising:
- a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in parallel with each other; and
a group of a first n-channel MOS transistor a second n-channel MOS transistor and a third n-channel MOS transistor which have channels connected in series with each other, wherein;
said p-channel MOS transistor group and said n-channel MOS transistor group are formed on a substrate having an SOI structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;
respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;
respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input;
respective gates of said third p-channel MOS transistor and said third n-channel MOS transistor are connected to a third input; and
a node between said p-channel MOS transistor group and said n-channel MOS transistor group is connected to an output, wherein each of said first p-channel MOS transistor, said second p-channel MOS transistor, said third p-channel MOS transistor, said first n-channel MOS transistor, said second n-channel MOS transistor and said third n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure. - View Dependent Claims (9)
- a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in parallel with each other; and
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10. A single-event-effect tolerant SOI-based 2-input NOR element comprising:
- a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in series with each other; and
a pair of a first n-channel MOS transistor and a second n-channel MOS transistor which have channels connected in parallel with each other, wherein;
said p-channel MOS transistor pair and said n-channel MOS transistor pair are formed on a substrate having an SOI structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;
respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;
respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input; and
a node between said p-channel MOS transistor pair and said n-channel MOS transistor pair is connected to an output, wherein each of the first p-channel MOS transistor, the second p-channel MOS transistor, the first n-channel MOS transistor and the second n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure. - View Dependent Claims (11)
- a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in series with each other; and
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12. A single-event-effect tolerant SOI-based 3-input NOR element comprising:
- a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in series with each other; and
a group of a first n-channel MOS transistor, a second n-channel MOS transistor and a third n-channel MOS transistor which have channels connected in parallel with each other, wherein;
said p-channel MOS transistor group and said n-channel MOS transistor group are formed on a substrate having an SOI structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;
respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;
respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input;
respective gates of said third p-channel MOS transistor and said third n-channel MOS transistor are connected to a third input; and
a node between said p-channel MOS transistor group and said n-channel MOS transistor group is connected to an output, wherein each of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor and the third n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure. - View Dependent Claims (13)
- a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in series with each other; and
Specification