LDMOS device and method for manufacturing the same

• US 20070069308A1
• Filed: 09/26/2006
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Ko, Choul
• Granted Patent: US 7,582,533 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.

Claims

1. A lateral diffused MOS device comprising:

a buried layer formed in a first conductive type substrate and doped with a second conductive type impurity;

a first well formed in the buried layer and doped with the first conductive type impurity;

a field insulator formed on a surface of the first well;

a gate insulating layer formed on a surface of the first well at both sides of the field insulator;

a second well formed in the first well at one side of the field insulator and doped with the first conductive type impurity;

a source region formed in a surface of the second well;

a drain region isolated from the source region and formed in the surface of the first well at the other side of the field insulator;

a gate electrode formed on the gate insulating layer on the source region;

a first field plate formed on a predetermined portion of the field insulator and connected with the gate electrode; and

a second field plate formed on another predetermined portion of the field insulator and spaced apart by a predetermined spacing from the first field plate.

2. The lateral diffused MOS device according to claim 1, wherein the gate electrode, the first field plate and the second field plate are formed of a same polysilicon material.

3. The lateral diffused MOS device according to claim 1, further comprising sidewall spacers formed on the gate electrode, the first field plate, and the second field plate.

4. The lateral diffused MOS device according to claim 1, wherein the first conductive type is P-type and the second conductive type is N-type.

5. The lateral diffused MOS device according to claim 1, further comprising a first doping region formed in the surface of the second well and doped with the first conductive type impurity.

6. The lateral diffused MOS device according to claim 1, wherein the gate insulating layer is formed on an entire surface of the substrate except for the field insulator.

7. The lateral diffused MOS device according to claim 1, wherein a bias applied to the second field plate is different from a bias applied to the first field plate.

8. The lateral diffused MOS device according to claim 1, wherein a bias applied to the second field plate is the same as a bias applied to the drain region.

9. The lateral diffused MOS device according to claim 1, wherein a bias applied to the second field plate is different from a bias applied to the gate electrode.

10. The lateral diffused MOS device according to claim 1, wherein the source region is doped with the second conductive type impurity.

11. A method for manufacturing a lateral diffused MOS device, the method comprising:

forming a buried layer doped with a second conductive type impurity in a first conductive type substrate;

forming a first well doped with the first conductive type impurity in the buried layer;

forming a field insulator on a surface of the first well;

forming a gate insulating layer on a surface of the first well at both sides of the field insulator;

forming a second well doped with the first conductive type impurity in the first well at one side of the field insulator;

forming a source region in a surface of the second well;

forming a drain region isolated from the source region in the surface of the first well at the other side of the field insulator;

forming a gate electrode on the gate insulating layer on the source region;

forming a first field plate connected with the gate electrode on a predetermined portion of the field insulator; and

forming a second field plate spaced apart by a predetermined spacing from the first field plate on another predetermined portion of the field insulator.

12. The method according to claim 11, wherein the gate electrode, the first field plate and the second field plate are formed at the same time.

13. The method according to claim 11, wherein the gate electrode, the first field plate and the second field plate are formed using a same mask.

14. The method according to claim 11, wherein the gate electrode, the first field plate and the second field plate are formed of a same polysilicon material.

15. The method according to claim 11, wherein forming the gate electrode, the first field plate, and the second field plate comprises:

forming a polysilicon layer on an entire surface of the substrate including the gate insulating layer and the field insulator;

forming a photoresist pattern exposing the polysilicon layer on a predetermined portion of the source region, the drain region and the field insulator; and

etching the polysilicon layer using the photoresist pattern as a mask.

16. The method according to claim 11, further comprising forming sidewall spacers on the gate electrode, the first field plate, and the second field plate.

17. The method according to claim 11, wherein the first conductive type is P-type and the second conductive type is N-type.

18. The method according to claim 11, further comprising forming a first doping region doped with the first conductive type impurity in the surface of the second well.

19. The method according to claim 11, wherein the source region is doped with the second conductive type impurity.

20. The method according to claim 11, wherein the second field plate is formed such that a bias applied to the second field plate is different from a bias applied to the first field plate.