Packaged die on PCB with heat sink encapsulant and methods

• US 20070069372A1
• Filed: 11/22/2006
• Published: 03/29/2007
• Est. Priority Date: 05/24/1996
• Status: Abandoned Application

• Current Assignee: James Wark, Salman Akram
• Original Assignee: James Wark, Salman Akram
• Inventors: Akram, Salman, Wark, James
• Application Number:
  US11/603,581
• Publication Number:
  US 20070069372A1
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Claims

1. An assembly method for a semiconductor assembly having a substrate and a semiconductor chip having a first surface and a second surface comprising:

attaching at least a portion of the first surface of the semiconductor chip to at least a portion of the substrate;

forming an electrical connection between the semiconductor chip and the substrate;

forming a wall substantially around a periphery of the second surface of the semiconductor chip using a barrier material, the wall around the periphery of the second surface of the semiconductor chip defining a recess, the barrier material having a first thermal conductivity;

extending the barrier material to contact the substrate; and

disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.

2. The method of claim 1, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.

3. The method of claim 1, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.

4. The method of claim 1, wherein the barrier material substantially encapsulates the at least one bond wire.

5. The method of claim 1, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.

6. The method of claim 5, wherein the barrier material substantially encapsulates the at least one tape automated bond.

7. The method of claim 1, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.

8. The method of claim 7, further comprising disposing an underfill encapsulant substantially between the semiconductor chip and the substrate.

9. A method of making a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising:

attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;

disposing an underfill material substantially between the substrate and each semiconductor chip;

forming an electrical connection between each semiconductor chip and the substrate;

forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;

extending the barrier material to contact and adhere to the substrate; and

disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.

10. The method of claim 9, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.

11. The method of claim 9, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.

12. The method of claim 11, wherein the barrier material substantially encapsulates the at least one bond wire.

13. The method of claim 11, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.

14. The method of claim 13, wherein the barrier material substantially encapsulates the at least one tape automated bond.

15. The method of claim 9, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.

16. A heat transfer method for a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising:

attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;

disposing an underfill material substantially between the substrate and each semiconductor chip;

forming an electrical connection between each semiconductor chip and the substrate;

forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;

extending the barrier material to contact and adhere to the substrate; and

disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.

17. The method of claim 16, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.

18. The method of claim 16, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.

19. The method of claim 18, wherein the barrier material substantially encapsulates the at least one bond wire.

20. The method of claim 18, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.

21. The method of claim 20, wherein the barrier material substantially encapsulates the at least one tape automated bond.

22. The method of claim 16, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.