CLOCK DISTRIBUTION NETWORKS AND CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS

• US 20070069377A1
• Filed: 11/14/2006
• Published: 03/29/2007
• Est. Priority Date: 04/18/2002
• Status: Abandoned Application

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Siniaguine, Oleg
• Application Number:
  US11/559,805
• Publication Number:
  US 20070069377A1
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Claims

1. A method for operating an integrated circuit, the integrated circuit comprising:

a trench in a semiconductor substrate;

a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;

a first conductive layer located between the conductive line and surfaces of the trench;

a first dielectric insulating the first conductive layer from the conductive line; and

a second dielectric between the first conductive layer and surfaces of the trench;

the method comprising holding the first conductive layer at a constant voltage while providing an alternating voltage on the conductive line when the integrated circuit is operated.

2. The method of claim 1 wherein the two nodes are located at two different ends of the conductive line.

3. The method of claim 1 wherein the trench is part of a trench network having conductive lines formed therein.

4. The method of claim 1 wherein the integrated circuit further comprises dielectric insulating the conductive line from the substrate.

5. The method of claim 1 wherein the first conductive layer is formed before the conductive line.

6. The method of claim 1 wherein the first conductive layer is present below a top surface of the conductive line.

7. The method of claim 1 wherein the first conductive layer is present below the conductive line above the trench'"'"'s bottom surface.

8. The method of claim 1 wherein the conductive line is part of a clock distribution network.

9. The method of claim 1 wherein the integrated circuit further comprises a third dielectric overlying the conductive line, and a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, with at least a portion of the second conductive layer lying directly above at least a portion of the conductive line, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.

10. The method of claim 9 wherein the second conductive layer crosses over the trench over the conductive line.

11. A manufacturing method comprising:

forming a trench in a semiconductor substrate; and

forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;

forming a first conductive layer located between the conductive line and surfaces of the trench;

forming a first dielectric insulating the first conductive layer from the conductive line; and

before forming the first conductive layer, forming a second dielectric between the first conductive layer and surfaces of the trench;

wherein the trench is part of a tree network of trenches, and the conductive line is part of a tree network of conductive lines.

12. The method of claim 11 wherein the first conductive layer is formed before the conductive line.

13. The method of claim 11 wherein the first conductive layer is present below a top surface of the conductive line.

14. The method of claim 11 wherein the first conductive layer is present below the conductive line above the trench'"'"'s bottom surface.

15. A manufacturing method comprising:

forming a trench in a semiconductor substrate; and

forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;

forming a first conductive layer located between the conductive line and surfaces of the trench;

forming a first dielectric insulating the first conductive layer from the conductive line; and

before forming the first conductive layer, forming a second dielectric between the first conductive layer and surfaces of the trench;

wherein the trench is part of a trench network comprising a grid of trenches, and the conductive line is part of a grid network of conductive lines.

16. The method of claim 15 wherein the first conductive layer is formed before the conductive line.

17. The method of claim 15 wherein the first conductive layer is present below a top surface of the conductive line.

18. The method of claim 15 wherein the first conductive layer is present below the conductive line above the trench'"'"'s bottom surface.

19. A method for operating an integrated circuit, the integrated circuit comprising:

a trench in a semiconductor substrate;

a conductive line in the trench;

a first conductive layer located between the conductive line and surfaces of the trench;

a first dielectric insulating the first conductive layer from the conductive line; and

a second dielectric between the first conductive layer and surfaces of the trench;

the method comprising holding the first conductive layer at a constant voltage while providing a clock signal on the conductive line when the integrated circuit is operated.

20. The method of claim 19 wherein the trench is part of a trench network having conductive lines formed therein which comprise said conductive line on which the clock signal is provided.

21. The method of claim 19 wherein the integrated circuit further comprises dielectric insulating the conductive line from the substrate.

22. The method of claim 19 wherein the first conductive layer is present below a top surface of the conductive line.

23. The method of claim 19 wherein the first conductive layer is present below the conductive line above the trench'"'"'s bottom surface.

24. The method of claim 19 wherein the integrated circuit further comprises a third dielectric overlying the conductive line, and a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, wherein the second conductive layer crosses over the trench over the conductive line, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.