Switch circuit for high-frequency-signal switching
First Claim
1. A switch circuit comprising:
- first and second input/output terminals;
first depletion-mode transistors serially-connected between first and second nodes, said first node being connected to said first input/output terminal, and said second node being connected to a connection node;
second depletion-mode transistors serially-connected between third and fourth nodes, said third node being connected to said second input/output terminal, and said fourth node being connected to said connection node;
a capacitor element connected between said connection node and selected one of said second and fourth nodes;
a common terminal connected to said connection node;
a bias circuit feeding a first bias voltage to gates of said first depletion-mode transistors, and feeding a second bias voltage to selected one of said third and fourth nodes; and
a switch control terminal receiving a control voltage, said switch control terminal being connected to gates of said second depletion-mode transistors, and to selected one of said first and second nodes, wherein said control voltage has a voltage level selected out of a higher power supply voltage and a lower power supply voltage, wherein said first bias voltage is higher than said lower power supply voltage, and wherein said second bias voltage is higher than said first bias voltage and lower than said higher power supply voltage.
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Accused Products
Abstract
A switch circuit includes first and second input/output terminals; first depletion-mode transistors serially-connected between first and second nodes; second depletion-mode transistors serially-connected between third and fourth nodes; a common terminal connected to a connection node; a bias circuit feeding a first bias voltage to gates of the first depletion-mode transistors, and feeding a second bias voltage to selected one of the third and fourth nodes; and a switch control terminal receiving a control voltage. The first node is connected to the first input/output terminal, while the third node is connected to the second input/output terminal. The second and fourth nodes are connected to the connection node. A capacitor element is connected between the connection node and selected one of the second and fourth nodes. The switch control terminal is connected to gates of the second depletion-mode transistors, and to selected one of the first and second nodes.
11 Citations
6 Claims
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1. A switch circuit comprising:
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first and second input/output terminals;
first depletion-mode transistors serially-connected between first and second nodes, said first node being connected to said first input/output terminal, and said second node being connected to a connection node;
second depletion-mode transistors serially-connected between third and fourth nodes, said third node being connected to said second input/output terminal, and said fourth node being connected to said connection node;
a capacitor element connected between said connection node and selected one of said second and fourth nodes;
a common terminal connected to said connection node;
a bias circuit feeding a first bias voltage to gates of said first depletion-mode transistors, and feeding a second bias voltage to selected one of said third and fourth nodes; and
a switch control terminal receiving a control voltage, said switch control terminal being connected to gates of said second depletion-mode transistors, and to selected one of said first and second nodes, wherein said control voltage has a voltage level selected out of a higher power supply voltage and a lower power supply voltage, wherein said first bias voltage is higher than said lower power supply voltage, and wherein said second bias voltage is higher than said first bias voltage and lower than said higher power supply voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification