Tamper monitor circuit

• US 20070069875A1
• Filed: 09/28/2005
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Corrent Corp.
• Inventors: Doi, Bryan
• Granted Patent: US 7,385,491 B2
• Time in Patent Office: Days
• US Class Current: 340/440
• CPC Class Codes: G06F 21/554 involving event detection and direct action

Abstract

A tamper monitor circuit detects voltage, temperature, and/or clock variations that may be associated with a circuit tampering technique, and triggers an appropriate tamper response. The tamper monitor circuit includes a reference oscillator, a detection oscillator, and a comparison circuit. The reference oscillator supplies a reference signal having a reference frequency. The detection oscillator operates at a circuit temperature and is energized with a supply voltage, and supplies a detection signal having a frequency that varies with variations in the circuit temperature, variations in the supply voltage, or both. The comparison circuit receives the reference signal and the detection signal and, in response to the reference signal, selectively determines the frequency of the detection signal, determines a frequency difference between two or more of the determined frequencies, and supplies a tamper detect signal if the determined frequency difference exceeds a predetermined difference threshold.

Claims

1. A tamper monitor circuit, comprising:

a reference oscillator operable to supply a reference signal having a reference frequency;

a detection oscillator configured to operate at a circuit temperature and to be energized with a supply voltage, the detection oscillator operable to supply a detection signal having a frequency that varies with variations in the circuit temperature, variations in the supply voltage, or both; and

a comparison circuit coupled to receive the reference signal and the detection signal and operable, in response to the reference signal, to (i) selectively determine the frequency of the detection signal, (ii) determine a frequency difference between two or more of the determined frequencies, and (iii) supply a tamper detect signal if the determined frequency difference exceeds a predetermined difference threshold.

2. The circuit of claim 1, wherein the comparison circuit comprises:

a detection counter coupled to receive the detection signal and operable to generate a detection count value representative of a number of detection signal periods; and

a detection count capture circuit coupled to the detection counter and configured to receive a count capture command, the count capture circuit operable, in response to the count capture command, to capture the detection count value.

3. The circuit of claim 2, wherein the comparison circuit further comprises:

a reference counter coupled to receive the reference signal and operable to generate a reference count value representative of a number of reference signal periods; and

a reference count comparator coupled to the reference counter, the reference count comparator operable to determine when the reference count value reaches a predetermined comparator count value and, upon determining that the reference count reaches the predetermined comparator count value, to supply the count capture command.

4. The circuit of claim 3, further comprising:

a controller circuit coupled to the reference count comparator circuit and operable to supply the predetermined comparator count value thereto.

5. The circuit of claim 4, wherein:

the detection count capture circuit is further operable, upon capturing the detection count value, to supply a count capture notification signal;

the controller circuit, in response to the count capture notification signal, retrieves the detection count value and supplies a counter clear signal;

the detection counter is coupled to receive the counter clear signal and is operable, in response thereto, to clear the detection count value; and

the reference counter is coupled to receive the counter clear signal and is operable, in response thereto, to clear the reference count value.

6. The circuit of claim 2, wherein the comparison circuit further comprises:

a controller circuit coupled to the detection count capture circuit and operable to (i) selectively retrieve the detection count value from the detection count capture circuit and (ii) compare the retrieved detection count value to a baseline detection count value.

7. The circuit of claim 6, wherein the controller circuit supplies the tamper detect signal if the retrieved detection count value differs from the baseline detection count value by a predetermined threshold magnitude.

8. The circuit of claim 6, wherein the controller circuit is further operable to selectively reset the baseline detection count value equal to the retrieved detection count value.

9. The circuit of claim 8, wherein the controller circuit resets the baseline detection count value if the retrieved detection count value differs from the baseline detection count value by a predetermined threshold magnitude.

10. The circuit of claim 9, wherein the controller circuit is further operable to:

determine a reset count representative of a number of times the baseline detection count value is reset; and

supply the tamper detect signal if the reset count exceeds a predetermined number.

11. The circuit of claim 6, wherein:

the controller circuit is further operable to supply a detection oscillator enable signal;

the detection oscillator is coupled to receive the detection oscillator enable signal and is operable, upon receipt thereof, to supply the detection signal.

12. The circuit of claim 11, wherein:

the detection count capture circuit is further operable, upon capturing the detection count value, to supply a count capture notification signal; and

the controller circuit, in response to the count capture notification signal, retrieves the detection count value and ceases supplying the detection oscillator enable signal, to thereby inhibit the detection oscillator from supplying the detection signal.

13. The circuit of claim 1, wherein:

the reference oscillator is configured to operate at a reference circuit temperature and is energized with the supply voltage;

the reference signal frequency varies, in accordance with a first sensitivity, with variations in the reference circuit temperature, the supply voltage, or both; and

the detection signal frequency varies, in accordance with a second sensitivity that differs from the first sensitivity, with variations in the circuit temperature, the supply voltage, or both.

14. A tamper monitor circuit, comprising:

a reference oscillator configured to operate at a first circuit temperature and to be energized with a supply voltage, the reference oscillator operable to supply a reference signal having a frequency that varies, in accordance with a first sensitivity, with variations in the first circuit temperature, variations in the supply voltage, or both; and

a detection oscillator configured to operate at a second circuit temperature and to be energized with the supply voltage, the detection oscillator operable to supply a detection signal having a frequency that varies, in accordance with a second sensitivity that differs from the first sensitivity, with variations in the second circuit temperature, variations in the supply voltage, or both; and

a comparison circuit coupled to receive the reference signal and the detection signal and operable, in response to the reference signal, to (i) selectively determine the frequency of the detection signal, (ii) determine a frequency difference between two or more of the determined frequencies, and (iii) supply a tamper detect signal if the determined frequency difference exceeds a predetermined difference threshold.

15. The circuit of claim 14, wherein the comparison circuit comprises:

a detection counter coupled to receive the detection signal and operable to generate a detection count value representative of a number of detection signal periods;

a reference counter coupled to receive the reference signal and operable to generate a reference count value representative of a number of reference signal periods;

a reference count comparator coupled to the reference counter, the reference count comparator operable to determine when the reference count value reaches a predetermined comparator count value and, upon determining that the reference count reaches the predetermined comparator count value, to supply a count capture command; and

a detection count capture circuit coupled to the detection counter and the reference count comparator, the detection count capture circuit coupled to receive the count capture command and operable, in response thereto, to capture the detection count value.

16. The circuit of claim 15, further comprising:

a controller circuit coupled to the reference count comparator circuit and operable to supply the predetermined comparator count value thereto.

17. The circuit of claim 15, wherein:

the detection count capture circuit is further operable, upon capturing the detection count value, to supply a count capture notification signal;

the controller circuit, in response to the count capture notification signal, retrieves the detection count value and supplies a counter clear signal;

the detection counter is coupled to receive the counter clear signal and is operable, in response thereto, to clear the detection count value; and

the reference counter is coupled to receive the counter clear signal and is operable, in response thereto, to clear the reference count value.

18. The circuit of claim 15, wherein the comparison circuit further comprises:

a controller circuit coupled to the detection count capture circuit and operable to (i) selectively retrieve the detection count value from the detection count capture circuit and (ii) compare the retrieved detection count value to a baseline detection count value.

19. The circuit of claim 18, wherein the controller circuit is further operable to:

reset the baseline detection count value if the retrieved detection count value differs from the baseline detection count value by a predetermined threshold magnitude;

determine a reset count representative of a number of times the baseline detection count value is reset; and

supply the tamper detect signal if the reset count exceeds a predetermined number.

20. A tamper monitor circuit, comprising:

a reference oscillator operable to supply a reference signal having a reference frequency;

a detection oscillator configured to operate at a circuit temperature and to be energized with a supply voltage, the detection oscillator operable to supply a detection signal having a frequency that varies with variations in the circuit temperature, variations in the supply voltage, or both;

a detection counter coupled to receive the detection signal and operable to generate a detection count value representative of a number of detection signal periods;

a reference counter coupled to receive the reference signal and operable to generate a reference count value representative of a number of reference signal periods;

a reference count comparator coupled to the reference counter, the reference count comparator operable to determine when the reference count value reaches a predetermined comparator count value and, upon determining that the reference count reaches the predetermined comparator count value, to supply a count capture command; and

a detection count capture circuit coupled to the detection counter and the reference count comparator, the detection count capture circuit coupled to receive the count capture command and operable, in response thereto, to capture the detection count value; and

a controller circuit coupled to the detection count capture circuit and operable to;

(i) selectively retrieve the detection count value from the detection count capture circuit,

(ii) compare the retrieved detection count value to a baseline detection count value, and

(iii) supply a tamper detect signal if the retrieved detection count value differs from the baseline detection count value by a predetermined threshold magnitude.