Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology

• US 20070070669A1
• Filed: 09/26/2005
• Published: 03/29/2007
• Est. Priority Date: 09/26/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Tsern, Ely
• Granted Patent: US 7,464,225 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15182 Fan-in arrangement of the internal vias
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.

Claims

1. A memory module comprising:

a connector interface;

a first signal path coupled to the connector interface;

a first integrated circuit memory die;

a first integrated circuit buffer die coupled to the first signal path, the first integrated circuit buffer die to receive control information from the first signal path, wherein the control information specifies an access to the first integrated circuit memory die such that the first integrated circuit memory die provides first data to the first integrated circuit buffer die in response to the control information;

a second integrated circuit memory die; and

a second integrated circuit buffer die coupled to the first signal path, the second integrated circuit buffer die to receive the control information from the first signal path, wherein the control information specifies an access to the second integrated circuit memory die such that the second integrated circuit memory die provides second data to the second integrated circuit buffer die in response to the control information.

2. The memory module of claim 1, further comprising:

a second signal path coupled to the first integrated circuit memory die and the first integrated circuit buffer device, wherein the second signal path is dedicated to carry the first data between the first integrated circuit memory die and first integrated circuit buffer device;

a third signal path coupled to the second integrated circuit memory die and the second integrated circuit buffer device, wherein the third signal path is dedicated to carry the second data between the second integrated circuit memory die and second integrated circuit buffer device;

a fourth signal path coupled to the first integrated circuit buffer device and the connector interface, wherein the fourth signal path is dedicated to carry the first data between the first integrated circuit buffer device and the connector interface; and

a fifth signal path coupled to the second integrated circuit buffer device and the connector interface, wherein the fifth signal path is dedicated to carry the second data between the second integrated circuit buffer device and the connector interface.

3. The memory module of claim 1, wherein the first signal path includes a signal line to provide a clock signal to the first integrated circuit buffer die and the second integrated circuit buffer die.

4. The memory module of claim 3, wherein

the first integrated circuit buffer die generates a second clock signal using the first clock signal and provides the second clock signal to the first integrated circuit memory die;

and

the second integrated circuit buffer die generates a third clock signal using the first clock signal and provides the third clock signal to the second integrated circuit memory die.

5. The memory module of claim 1, wherein the first signal path includes a first signal line to provide a first clock signal to the first integrated circuit buffer die and a second clock signal to the second integrated circuit buffer die.

6. The memory module of claim 1, wherein the first integrated circuit buffer die is disposed in a first package and the first integrated circuit memory die is disposed in a second package, and wherein the second integrated circuit buffer die is disposed in a third package and the second integrated circuit memory die is disposed in a fourth package.

7. The memory module of claim 6, wherein the first package is stacked upon the second package.

8. The memory module of claim 6, wherein a fifth package includes a third integrated circuit memory die, and wherein the fifth package is stacked upon the first package.

9. The memory module of claim 6, wherein the first package is stacked upon the second package, and wherein a fifth package includes a third integrated circuit memory die, and wherein the fifth package is stacked upon the first package.

10. The memory module of claim 1, wherein the first integrated circuit buffer die and the first integrated circuit memory die are disposed in a first common package, and wherein the second integrated circuit buffer die and the second integrated circuit memory die are disposed in a second common package.

11. The memory module of claim 1, comprising:

a signal line in the first signal path to provide a clock signal from the first integrated circuit buffer die to the connector interface; and

a second signal path coupled to the first integrated circuit buffer device and the connector interface, the second signal path to carry the first data between the first integrated circuit buffer device and the connector interface wherein the first data propagates in accordance with a temporal relationship to the clock signal.

12. The memory module of claim 1, comprising:

a second signal path coupled to the first integrated circuit buffer device and the connector interface, the second signal path to carry the first data between the first integrated circuit buffer device and the connector interface wherein the first data propagates in accordance with a temporal relationship to a clock signal; and

a first signal line in the second signal path to provide the clock signal.

13. The memory module of claim 1, comprising:

a second signal path coupled to the first integrated circuit buffer device and the connector interface, the second signal path to carry the first data between the first integrated circuit buffer device and the connector interface wherein the first data propagates in accordance with a temporal relationship to a strobe signal; and

a first signal line in the second signal path to provide the strobe signal.

14. The memory module of claim 13, wherein the strobe signal is bidirectional.

15. The memory module of claim 13, wherein the strobe signal is unidirectional.

16. The memory module of claim 1, comprising:

a signal line in the first signal path to provide a clock signal to the first integrated circuit buffer die from the connector interface;

a second signal path coupled to the first integrated circuit buffer device and the connector interface; and

a signal line in the second signal path to provide write data to be stored in the first integrated circuit memory die via the first integrated circuit buffer die, wherein the write data has a temporal relationship with the clock signal.

17. The memory module of claim 1, comprising:

a second signal path coupled to the first integrated circuit buffer device and the connector interface;

a signal line in the second signal path to provide a clock signal to the first integrated circuit buffer die from the connector interface; and

a signal line in the second signal path to provide write data to be stored in the first integrated circuit memory die from the connector interface via the first integrated circuit buffer die, wherein the write data has a temporal relationship with the clock signal.

18. The memory module of claim 1, comprising:

a second signal path coupled to the first integrated circuit buffer device and the connector interface;

a signal line in the second signal path to provide a strobe signal to the first integrated circuit buffer die from the connector interface; and

a signal line in the second signal path to provide write data to be stored in the first integrated circuit memory die from the connector interface via the first integrated circuit buffer die, wherein the write data has a temporal relationship with the strobe signal.

19. The memory module of claim 18, wherein the strobe signal is bidirectional.

20. The memory module of claim 18, wherein the strobe signal is unidirectional.

21. The memory module of claim 1, further comprising:

a termination coupled to the first signal path.

22. The memory module of claim 21, wherein the termination is disposed on the memory module.

23. The memory module of claim 21, wherein the termination is disposed on the first integrated circuit buffer die.

24. The memory module of claim 21, wherein the termination is disposed in a package housing the first integrated circuit buffer die.

25. The memory module of claim 1, further comprising:

a second signal path coupled to the first integrated circuit memory die and the first integrated circuit buffer device, the second signal path is to carry the first data between the first integrated circuit memory die and first integrated circuit buffer device;

a third signal path coupled to the second integrated circuit memory die and the second integrated circuit buffer device, the third signal path to carry the second data between the second integrated circuit memory die and second integrated circuit buffer device;

a first termination coupled the second signal path; and

a second termination coupled to the third signal path.

26. The memory module of claim 25, wherein the first termination is disposed on the memory module and the second termination is disposed on the memory module.

27. The memory module of claim 25, wherein the first termination is disposed on the first integrated circuit buffer die and the second termination is disposed on the second integrated circuit buffer die.

28. The memory module of claim 25, wherein the first termination is disposed on a package housing the first integrated circuit buffer die and the second termination is disposed on a package housing the second integrated circuit buffer die.

29. The memory module of claim 1, wherein the first integrated circuit buffer die is disposed in a first package and the first integrated circuit memory die is disposed in a second package,

wherein the second integrated circuit buffer die is disposed in a third package and the second integrated circuit memory die is disposed in a fourth package,

wherein the first and second packages are disposed on a first side of the memory module, and

wherein the third and fourth packages are disposed on a second side of the memory module.

30. The memory module of claim 1, wherein the first integrated circuit memory die includes a memory array having a first type of storage cells and the second integrated circuit memory die includes a memory array having a second type of storage cells, wherein the first type of storage cells is different than the second type of storage cells.

31. The memory module of claim 1, wherein:

the first and second integrated circuit buffer dies receive the control information in a DDR3 format;

the first integrated circuit buffer die provides DDR2 control signals corresponding to the control information to the first integrated buffer die; and

the second integrated circuit buffer die provides DDR2 control signals corresponding to the control information to the second integrated circuit memory die.

32. The memory module of claim 1, wherein the first and second integrated circuit buffer dies receive the control information in the form of a first type of signal and provide control signals to the respective first and second integrated circuit memory dies in the form of a second type of signal, wherein the first type of signal is different that the second type of signal.

33. The memory module of claim 1, wherein the first and second integrated circuit buffer dies receive the first and second control information in a first protocol format and provide control signals to the first and second integrated circuit memory dies in a second protocol format, wherein the first protocol format is different that the second protocol format.

34. The memory module of claim 1, wherein the first and second integrated circuit buffer dies includes logic to emulate a function of the first and second memory dies.

35. The memory module of claim 1, further comprising:

at least one non-volatile storage location to store information pertaining to a configuration of the memory module.

36. A memory module comprising:

an interface;

a first package including a buffer and an integrated circuit memory device having a memory array, wherein the buffer of the first package is coupled to the interface;

a second package including a buffer and an integrated circuit memory device having a memory array, wherein the buffer of the second package is coupled to the interface; and

at least a first non-volatile storage location to store information pertaining to a configuration of the memory module.

37. The memory module of claim 36, wherein the at least first non-volatile storage location is a serial presence detect device and the information includes at least the number of integrated circuit memory devices included in the memory module and timing information of the integrated circuit memory devices.

38. The memory module of claim 36, wherein the at least first non-volatile storage location is included in the first package and at least a second non-volatile storage location containing the information is included in the second package.

39. The memory module of claim 36, wherein the at least first non-volatile storage location is included in the first package.

40. The memory module of claim 36, wherein the at least first non-volatile storage location is included in a third package disposed on the memory module.

41. The memory module of claim 36, wherein the information includes at least information to repair the integrated circuit memory device of the first package.

42. The memory module of claim 36, wherein the buffer of the first package reads the information stored in the at least first non-volatile storage location.

43. The memory module of claim 36, wherein the buffer of the first package writes the information stored in the at least first non-volatile storage location.

44. The memory module of claim 36, wherein the information is transferred between the interface and the at least first non-volatile storage location.

45. A memory module comprising:

a connector interface;

a first signal path coupled to the connector interface;

a first integrated circuit memory die;

a second integrated circuit memory die;

a first integrated circuit buffer die coupled to the first signal path, the first integrated circuit buffer die to receive first control information from the first signal path, wherein the first control information specifies an access to the first integrated circuit memory die;

a second integrated circuit buffer die coupled to the first signal path, the second integrated circuit buffer die to receive second control information from the first signal path, wherein the second control information specifies an access to the second integrated circuit memory die; and

a signal line to provide a first clock signal to the first integrated circuit buffer die and the second integrated circuit buffer die, wherein;

the first integrated circuit buffer die generates a second clock signal using the first clock signal and provides the second clock signal to the first integrated circuit memory die; and

the second integrated circuit buffer die generates a third clock signal using the first clock signal and provides the third clock signal to the first integrated circuit memory die.