Circuitry for a programmable element

• US 20070070679A1
• Filed: 11/13/2006
• Published: 03/29/2007
• Est. Priority Date: 09/11/2001
• Status: Active Grant

• Current Assignee: Timothy Cowles
• Original Assignee: Timothy Cowles
• Inventors: Cowles, Timothy
• Granted Patent: US 7,450,450 B2
• Time in Patent Office: Days
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals

Abstract

As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Claims

1. A packaged circuit, comprising:

a wire;

a first pad bonded to the wire;

a second pad unbonded to any wire; and

a programmable element directly coupled to the second pad and indirectly coupled to the first pad.

2. The packaged circuit in claim 1, further comprising a transistor coupled to the programmable element and the first pad, wherein the transistor is positioned to regulate electrical communication between the programmable element and the fast pad.

3. Circuitry for a die, comprising:

a first terminal on the die and located to receive a plurality of voltage signals from at least one source external to the die;

a second terminal on the die and located to receive a plurality of voltage signals from at least one source external to the die;

an anti-fuse; and

a node in unregulated electrical communication with the first terminal and the anti-fuse, the node being in regulated electrical communication with the second terminal.

4. A circuit for a semiconductor die, comprising:

a first pad on the semiconductor die, wherein the first pad is configured to receive at least a first external voltage;

a transistor coupled to the first pad; and

a second pad coupled to the first pad through the transistor, wherein the second pad is configured to receive at least a second external voltage.

5. The circuit in claim 4, further comprising a programming device coupled to the second pad.

6. The circuit in claim 5, wherein the programming device is coupled to the first pad through the transistor.

7. Memory circuitry, comprising:

an equilibration circuit;

a first contact pad coupled to the equilibration circuit;

a memory control circuit;

a second contact pad coupled to the memory control circuit;

an anti-fuse circuit comprising;

a voltage node coupled to the first contact pad,

an anti-fuse coupled to the voltage node, and

at least one transistor coupled between the anti-fuse and ground;

a pass gate coupled between the voltage node and the second contact pad; and

a capacitor coupled to the pass gate.

8. The memory circuitry of claim 7, further comprising:

a voltage regulation device coupled to the anti-fuse circuit; and

a latch circuit coupled to the voltage regulation device.

9. Electrical communication devices for programmable circuitry within a packaged part, wherein the part includes a latch circuit and a bonded pad, comprising:

an unbonded pad within the packaged part, wherein the pad is directly coupled to the programmable circuitry; and

a first transistor directly coupled to the programmable circuitry and between the programmable circuitry and the latch circuit.

10. The electrical communication devices in claim 9, further comprising a second transistor directly coupled to the programmable circuitry and between the programmable circuitry and the bonded pad.

11. A computer system, comprising:

a microprocessor,

a clock circuit coupled to the microprocessor; and

a circuit device coupled to the microprocessor and comprising;

a programmable element, and

a conductive terminal directly coupled to the programmable element.

12. The computer system of claim 11, wherein the conductive terminal is electrically isolated from the microprocessor and the clock circuit.

13. The computer system of claim 11, wherein the circuit device is a memory device.

14. The computer system of claim 11, wherein the programmable element is an anti-fuse.

15. A method of configuring a semiconductor die, comprising:

sharing a die terminal between a first device on the die and a second device on the die, wherein the first device is configured to receive a voltage through the die terminal;

allowing unregulated electrical communication between the die terminal and the second device, wherein an act of determining a status of the second device while the voltage is present at the die terminal may result in an incorrect determination of the status; and

preventing the act of determining while the voltage is present at the die terminal.

16. The method in claim 15, further comprising:

including a circuit on the die, wherein the circuit is configured to perform the act of determining; and

isolating the circuit from the second device while the voltage is present.

17. The method in claim 16, wherein the isolating act comprises:

electrically interposing a transistor between the circuit and the second device; and

preventing electrical communication between the circuit and the second device using the transistor.

18. The method in claim 17, wherein the act of preventing electrical communication comprises turning off the transistor in direct response to the voltage being present at the die terminal.

19. The method in claim 18, wherein the sharing act comprises sharing a die terminal between an equilibration circuit and an anti-fuse, wherein the equilibration circuit is configured to receive a margin-testing voltage through the die terminal.

20. A method of protecting a latch circuit from receiving a voltage from a voltage source through an anti-fuse circuit after an anti-fuse-blowing mode of the circuit, the method comprising:

electrically interposing a device between the latch circuit and the anti-fuse circuit, wherein the device is configured to selectively block electrical communication therebetween; and

blocking all electrical communication between the latch circuit and the anti-fuse circuit, wherein the blocking act occurs outside of the anti-fuse-blowing mode and while the voltage is present at the anti-fuse circuit.

21. The method in claim 20, further comprising refraining from interposing any device between the voltage source and the anti-fuse that is configured to selectively block electrical communication therebetween.

22. A method of regulating the voltage transmitted through an anti-fuse to a circuit, the method comprising:

providing a first voltage regulator between the anti-fuse and the circuit, wherein the voltage regulator is configured to discourage electrical communication therethrough when inactivated; and

inactivating the first voltage regulator when a voltage is transmitted to the anti-fuse, wherein no other voltage regulator is present between a first source of the voltage and the anti-fuse.

23. The method in claim 22, further comprising inactivating the first voltage regulator when a voltage is transmitted to the anti-fuse, wherein a second voltage regulator is present between a second source of the voltage and the anti-fuse, and wherein the second voltage regulator allows electrical communication therethrough.

24. The method in claim 23, wherein:

said method further comprises at most partially activating the first voltage regulator when a low voltage is transmitted to the anti-fuse; and

said act of inactivating the first voltage regulator when a voltage is transmitted to the anti-fuse, wherein no other voltage regulator is present between a first source of the voltage and the anti-fuse comprises;

inactivating the first voltage regulator when a high voltage is transmitted.