STORAGE DEVICE AND SEMICONDUCTOR DEVICE

• US 20070070682A1
• Filed: 09/11/2006
• Published: 03/29/2007
• Est. Priority Date: 09/12/2005
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Okazaki, Nobumichi, Nakashima, Chieko, Hachino, Hidenari, Nagao, Hajime
• Granted Patent: US 7,471,543 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R≧V/I.

Claims

1. A storage device comprising:

a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from said first threshold voltage, and a circuit element connected in series with said storage element,

wherein letting R be a resistance value of said storage element after writing, V be said second threshold voltage, and I be a current that can be passed through said storage element at a time of erasure, R≧

V/I.

2. The storage device as claimed in claim 1, wherein:

said circuit element is a unipolar transistor; and

the current that can be passed through said storage element at a time of erasure is a saturation current of said unipolar transistor.

3. The storage device as claimed in claim 1, wherein:

said circuit element is a unipolar transistor; and

the current that can be passed through said storage element at a time of erasure is a maximum value of a drain current of said unipolar transistor when said second threshold voltage is applied to said storage element.

4. A storage device comprising:

a plurality of memory cells each having a storage element formed by interposing a storage layer between a first electrode layer and a second electrode layer, said storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage between the first electrode layer and the second electrode layer, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from said first threshold voltage, and a circuit element connected in series with said storage element,

wherein letting R be a resistance value of said storage element after writing, V be said second threshold voltage, and I be a current that can be passed through said storage element at a time of erasure, R≧

V/I.

5. The storage device as claimed in claim 4, wherein:

said circuit element is a unipolar transistor; and

the current that can be passed through said storage element at a time of erasure is a saturation current of said unipolar transistor.

6. The storage device as claimed in claim 4, wherein:

said circuit element is a unipolar transistor; and

the current that can be passed through said storage element at a time of erasure is a maximum value of a drain current of said unipolar transistor when said second threshold voltage is applied to said storage element.

7. The storage device as claimed in claims 4,

wherein at least one of the electrode layers of said memory cell is formed by a common electrode layer.

8. A semiconductor device comprising:

a storage device including a memory cell, said memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from said first threshold voltage, and a circuit element connected in series with said storage element; and

a writing control circuit for, letting R be a resistance value of said storage element after writing, V be said second threshold voltage, and I be a current that can be passed through said storage element at a time of erasure, making R≧

V/I.

9. The semiconductor device as claimed in claim 8,

wherein said writing control circuit is formed by a word line voltage setting circuit for limiting word line voltage.

10. The semiconductor device as claimed in claim 8,

wherein said writing control circuit is formed by a current limiting circuit for limiting current flowing through one of a bit line or a source line.

11. The semiconductor device as claimed in claim 8,

wherein said writing control circuit is a pulse driving circuit for limiting pulse widths of pulse signals applied to a word line and one of a bit line or a source line.

12. A semiconductor device comprising:

a storage device including a plurality of memory cells each having a storage element formed by interposing a storage layer between a first electrode layer and a second electrode layer, said storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage between the first electrode layer and the second electrode layer, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from said first threshold voltage, and a circuit element connected in series with said storage element; and

writing control means for, letting R be a resistance value of said storage element after writing, V be said second threshold voltage, and I be a current that can be passed through said storage element at a time of erasure, making R≧

V/I.

13. The semiconductor device as claimed in claim 12,

wherein said writing control circuit is formed by a word line voltage setting circuit for limiting word line voltage.

14. The semiconductor device as claimed in claim 12,

wherein said writing control circuit is formed by a current limiting circuit for limiting current flowing through one of a bit line or a source line.

15. The semiconductor device as claimed in claim 12,

wherein said writing control circuit is a pulse driving circuit for limiting pulse widths of pulse signals applied to a word line and one of a bit line or a source line.

16. The semiconductor device as claimed in claims 12,

wherein at least one of the electrode layers of said memory cell is formed by a common electrode layer.