Flash memory array system including a top gate memory cell

• US 20070070703A1
• Filed: 09/26/2005
• Published: 03/29/2007
• Est. Priority Date: 09/26/2005
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Nguyen, Hung, Ly, Anh, Hsueh, Sheng-Hsiung, Choi, Steve, Nguyen, Sang, Tran, Hieu, Hoang, Loc, Vu, Thuan
• Granted Patent: US 7,567,458 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Claims

1. A memory system comprising:

a plurality of memory cells arranged in sectors, each memory cell having a top gate; and

a control circuit coupled to the plurality of memory cells to control the disabling of top gates of memory cells that are defective.

2. The memory system of claim 1 wherein the memory cells are tip erased memory cells.

3. The memory system of claim 1 wherein the memory cells are source side injection memory cells.

4. The memory system of claim 1 wherein the memory cells are multilevel memory cells.

5. A memory system comprising:

a plurality of memory cells arranged in sectors, top gates of memory cells In a sector being coupled to a first line, source lines of memory cells in a sector being coupled to a second line.

6. The memory system of claim 5 wherein the memory cells are multilevel memory cells.

7. The memory system of claim 5 wherein the memory cells are tip erased memory cells

8. The memory system of claim 5 wherein the memory cells are source side injection memory cells.

9. The memory system of claim 8, wherein each memory cell further comprising:

a floating gate,

a select gate,

wherein said floating gate having a tip adjacent to said select gate for erasing said floating gate through said tip to said select gate.

10. The memory system of claim 8, wherein each memory cell further comprising:

a floating gate,

wherein said floating gate having a tip adjacent to said top gate for erasing said floating gate through said tip to said top gate.

11. A memory system comprising:

a plurality of memory cells arranged in sectors, source lines of memory cells in a sector being coupled to a first line and top gate lines of memory cells in said sector being coupled to individual lines.

12. The memory system of claim 11 wherein the memory cells are multilevel memory cells.

13. The memory system of claim 11 further comprising:

a plurality of word lines coupled to at least one other individual line.

14. The memory system of claim 11 wherein the memory cells are tip erased memory cells.

15. The memory system of claim 11 wherein the memory cells are source side injection memory cells.

16. A memory system comprising:

a plurality of memory cells arranged in sectors, the top gates of a first group of memory cells in a sector being coupled to a first line, source lines of a second group of memory cells in a sector being coupled to a second line, the top gates of a third group of memory cells in a sector being coupled to a third line, source lines of a fourth group of memory cells in a sector being coupled to a fourth line, the first group including memory cells in the second and fourth groups, the third group Including memory cells In the second and fourth groups, but not in the first group.

17. The memory system of claim 16 wherein the memory cells are multilevel memory cells.

18. A memory system comprising:

a plurality of memory cells arranged in sectors,

a plurality of decoders, each decoder having a latched signal disabling the application of low voltages signals to memory cells having a defective top gate in a corresponding sector.

19. The memory system of claim 18 wherein said latched signal is latched at power up recall.

20. The memory system of claim 18 wherein the memory cells are multilevel memory cells.

21. The memory system of claim 18 wherein each decoder includes a low voltage decoder for applying low voltage signals to memory cells in a corresponding sector.

22. The memory system of claim 21 wherein the memory cells are multilevel memory cells.

23. The memory system of claim 21 wherein each low voltage decoder includes a latch to disable said applying In response to a defective top gate.

24. The memory system of claim 21 wherein the low voltage decoder includes a current limiter on a top gate line for said memory cells.

25. The memory system of claim 24 wherein the memory cells are multilevel memory cells.

26. The memory system of claim 18 wherein each decoder includes a high voltage decoder for applying high voltage signals to memory cells in a corresponding sector.

27. The memory system of claim 26 wherein the memory cells are multilevel memory cells.

28. The memory system of claim 26 wherein each high voltage decoder includes a latch to disable said applying in response to a defective top gate.

29. The memory system of claim 28 wherein each high voltage decoder includes a latch to disable said applying in response to a defective word line.

30. A memory system comprising:

a plurality of memory cells arranged in sectors, each memory cell including a top gate and a source, a top gate line coupling memory cells in a sector, a word line coupling memory cells together, the top gate line being dynamically coupled to the word line.

31. The memory system of claim 30 wherein the memory cells are multilevel memory cells.

32. The memory system of claim 30 further comprising a first weak driver for driving the word line, and a second weak driver for driving the top gate line.

33. The memory system of claim 30 wherein the top gate line is floating.

34. A method comprising:

determining whether a memory cell has a good top gate and a good wordline;

selecting a redundant memory cell in the event that said memory cell does not have a good top gate and a good wordline;

verifying said memory cell or selected redundant memory cell; and

programming said memory cell or selected redundant memory cell In the event that said cell is not verified.

35. The method of claim 34 wherein said programming includes one terminal of said memory cell or bias thereof is fixed or incremental.

36. The method of claim 35 wherein said programming includes other terminals of said memory cell or biases being fixed or incremental.

37. The method of claim 34 wherein said memory cells are source side injection memory cells.

38. The method of claim 34 wherein said memory cells are tip erased memory cells.

39. A method comprising:

determining whether a memory cell has a good top gate;

selecting a redundant memory cell in the event that said memory cell does not have a good top gate;

verifying said memory cell or selected redundant memory cell; and

programming said memory cell or selected redundant memory cell in the event that said cell is not verified

40. The method of claim 39 wherein said programming includes one terminal of said memory cell or bias thereof is fixed or incremental.

41. The method of claim 40 wherein said programming includes other terminals of said memory cell or biases being fixed or incremental.

42. The method of claim 39 wherein said memory cells are source side injection memory cells.

43. The method of claim 39 wherein said memory cells are tip erased memory cells.