NONVOLATILE SEMICONDUCTOR MEMORY, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR INTEGRATED CIRCUITS AND SYSTEMS

• US 20070070708A1
• Filed: 11/14/2006
• Published: 03/29/2007
• Est. Priority Date: 02/05/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hashimoto, Koji, Shirota, Riichiro, Takeuchi, Yuji, ICHIGE, Masayuki, Sakui, Koji, Kuji, Tatsuaki, Mori, Seiichi
• Granted Patent: US 7,498,630 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Claims

1. (canceled)

2. A nonvolatile semiconductor memory embedded in a card operable so as to receive and transfer a predetermined signal from an external device, and the nonvolatile semiconductor memory comprising:

a plurality of word lines disposed in a row direction;

a plurality of bit lines disposed in a column direction perpendicular to the word lines;

memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;

a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and

a first select gate line connected to each of the gate electrodes of the first select transistors, wherein

the plurality of the word lines have a wiring line width which is the same as the first select gate line.

3. The nonvolatile semiconductor memory of claim 2, wherein a signal line DAT, a command line enable signal line CLE, an address line enable signal line ALE, and a ready/busy signal line R/B are connected to the card.

4. The nonvolatile semiconductor memory of claim 3, wherein the signal line DAT transfers a data signal, an address signal, or a command signal, the command line enable signal line CLE transmits a signal which indicates that the command signal is being transferred over the signal line DAT, the address line enable signal line ALE transmits a signal which indicates that the address signal is being transferred over the signal line DAT, and the ready/busy signal line R/B transmits a signal which indicates whether or not the nonvolatile semiconductor memory is ready.

5. The nonvolatile semiconductor memory of claim 2, wherein the card further comprises a controller.

6. The nonvolatile semiconductor memory of claim 5, wherein the controller controls the nonvolatile semiconductor memory and transfers a prescribed signal with the external device.

7. The nonvolatile semiconductor memory of claim 5, wherein the controller comprises an input and an output interface units (I/F), a microprocessor unit (MPU), and a buffer RAM.

8. The nonvolatile semiconductor memory of claim 5, wherein the output interface unit comprises an error correction code unit (ECC).

9. The nonvolatile semiconductor memory of claim 7, wherein the input interface unit transfers the prescribed signal to the external device, and the output interface unit transfers the prescribed signal to the nonvolatile semiconductor memory, the microprocessor unit (MPU) converts a logic address to a physical address, the buffer RAM temporarily stores data, and the error correction code unit (ECC) generates an error correction code.

10. The nonvolatile semiconductor memory of claim 7, wherein a command line CMD, and a clock signal line CLK are connected to the card.

11. The nonvolatile semiconductor memory of claim 7, wherein the card implements a system LSI chip by integrating the input and output interface units (I/F), the microprocessor unit (MPU), the buffer RAM, the error correction code unit (ECC) included in the output interface unit (I/F), and the nonvolatile semiconductor memory all onto one chip.

12. A nonvolatile semiconductor memory formed in a mixed memory loading microprocessor unit (MPU) embedded in a card, and the nonvolatile semiconductor memory comprising:

a plurality of word lines disposed in a row direction;

a plurality of bit lines disposed in a column direction perpendicular to the word lines;

memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;

a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and

a first select gate line connected to each of the gate electrodes of the first select transistors, wherein

the plurality of the word lines have a wiring line width which is the same as the first select gate line.

13. The nonvolatile semiconductor memory of claim 12, wherein the card implements a system LSI chip by integrating the input and output interface units (I/F), the mixed memory loading microprocessor unit (MPU), the buffer RAM, and the error correction code unit (ECC) included in the output interface unit (I/F) all onto one chip.

14. A nonvolatile semiconductor memory formed in a microprocessor unit (MPU) embedded in a card comprising:

a plurality of word lines disposed in a row direction;

a plurality of bit lines disposed in a column direction perpendicular to the word lines;

memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;

a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and

a first select gate line connected to each of the gate electrodes of the first select transistors, wherein

the plurality of the word lines have a wiring line width which is the same as the first select gate line.

15. The nonvolatile semiconductor memory of claim 14, wherein the microprocessor unit (MPU) further comprises, a ROM, a RAM, and a CPU.

16. The nonvolatile semiconductor memory of claim 15, the card further comprises a plane terminal coupled to the microprocessor unit (MPU).

17. The nonvolatile semiconductor memory of claim 15, wherein the card is connected to an external device via the plane terminal.

18. The nonvolatile semiconductor memory of claim 15, wherein the CPU comprises a calculation section and a control section.

19. The nonvolatile semiconductor memory of claim 18, wherein the control section is coupled to the nonvolatile semiconductor memory, the ROM, and the RAM.

20. The nonvolatile semiconductor memory of claim 15, wherein the card implements a system LSI chip by integrating the ROM, the RAM, the CPU, and the nonvolatile semiconductor memory all onto one chip.

21. The nonvolatile semiconductor memory of claim 15, wherein the ROM is coupled to the nonvolatile semiconductor memory to form an overall EEPROM mode flash memory.