Data input/output multiplexer of semiconductor device

• US 20070070712A1
• Filed: 09/29/2006
• Published: 03/29/2007
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Shin, Beom-Ju
• Granted Patent: US 7,577,038 B2
• Time in Patent Office: Days
• US Class Current: 365/189.20
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Claims

1. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line, comprising:

a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line; and

a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

2. The multiplexer of claim 1, further comprising a first multiplexer control signal generator for controlling the first multiplexer.

3. The multiplexer of claim 2, wherein the second multiplexer is driven by a control signal containing a data option signal.

4. A semiconductor device, comprising:

a data input/output (I/O) pad for receiving data;

a first input multiplexer for multiplexing the data inputted through the data I/O pad and supplying a first multiplexed data to a global I/O line, wherein the first input multiplexer is located between the data I/O pad and the global I/O line; and

a second input multiplexer for multiplexing the first multiplexed data supplied to the global I/O line and supplying a second multiplexed data to a local input/output (I/O) line, wherein the second input multiplexer is disposed between the global I/O line and the local I/O line.

5. The semiconductor device of claim 4, further comprising a first multiplexer control signal generator for controlling the first input multiplexer.

6. The semiconductor device of claim 5, wherein the second input multiplexer is driven by a control signal containing a data option signal.

7. The semiconductor device of claim 4, further comprising a data input sense amplifier for sensing and amplifying a signal supplied to the data I/O pad to provide the amplified signal to the first input multiplexer.

8. The semiconductor device of claim 4, further comprising a write driver for driving the output of the second input multiplexer to provide it to the local I/O line.

9. A semiconductor device, comprising:

a local I/O line;

a first output multiplexer for multiplexing data inputted to the local I/O line and supplying a first multiplexed data to the global I/O line, wherein the first output multiplexer is formed between the local I/O line and the global I/O line; and

a second output multiplexer for multiplexing the first multiplexed data supplied to the global I/O line and providing a second multiplexed data to the data I/O pad, wherein the second output multiplexer is located between the global I/O line and the data I/O pad.

10. The semiconductor device of claim 9, further comprising a first multiplexer control signal generator for controlling the first output multiplexer.

11. The semiconductor device of claim 10, wherein the second output multiplexer is driven by a control signal containing a data option signal.

12. The semiconductor device of claim 9, further comprising a sense amplifier for sensing and amplifying a signal supplied to the local I/O line to provide the amplified signal to the first output multiplexer.

13. The semiconductor device of claim 9, further comprising a pipe latch for latching the output signal of the second output multiplexer and providing the latched signal to the data I/O pad.