Semiconductor memory device for controlling reservoir capacitor

• US 20070070724A1
• Filed: 09/26/2006
• Published: 03/29/2007
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jang, Chae-Kyu
• Granted Patent: US 7,606,103 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor memory device is provided. Especially, there is disclosed a technique capable of increasing a net die by employing a cell capacitor as a reservoir capacitor according to a set mode. The semiconductor memory device of the present invention uses the cell capacitor as the reservoir capacitor in a normal mode, and prevents each voltage from being applied to the cell capacitor in a burn-in test mode. The voltage applied to the cell capacitor or MOS transistor can be adjusted according to the set mode.

Claims

1. A semiconductor memory device comprising:

a power supply unit for receiving and delivering a power supply voltage;

a reservoir capacitor for storing the power supply voltage provided from the power supply unit; and

a mode controller for selectively disconnecting the power supply unit from the reservoir capacitor depending on whether a current operation mode is a normal mode or a test mode.

2. The semiconductor memory device as recited in claim 1, wherein the mode controller includes a voltage controller for changing a voltage level applied to an electrode film of the reservoir capacitor.

3. The semiconductor memory device as recited in claim 1, wherein the reservoir capacitor is arranged in a peripheral region of the semiconductor memory device.

4. A semiconductor memory device comprising;

a plurality of reservoir capacitors;

a first power supply unit, arranged to correspond to the plurality of reservoir capacitors, for controlling a supply of a plurality of first voltages with different levels;

a mode controller for outputting a mode selection signal having a different state depending on a combination of a plurality of control signals for mode setting; and

a connection unit for connecting the plurality of first voltages to one terminal of the corresponding reservoir capacitors in response to the mode selection signal, respectively.

5. The semiconductor memory device as recited in claim 4, wherein each of the plurality of reservoir capacitors receives the corresponding first voltage through the first power supply unit in a normal mode, and halts receipt of the first voltage under the control of the mode controller in a burn-in test mode.

6. The semiconductor memory device as recited in claim 4, wherein the first power supply unit selectively supplies one of an external power supply voltage, a core voltage, a peripheral voltage, a cell array applying voltage, and a delay locked loop driving voltage.

7. The semiconductor memory device as recited in claim 4, further comprising a second power supply unit for selecting one of a plurality of second voltages with different levels in response to the mode selection signal and supplying the selected one terminal to the other of the plurality of reservoir capacitors, respectively.

8. The semiconductor memory device as recited in claim 7, wherein the second power supply unit selectively supplies one of a ground voltage, a cell array applying voltage, a bit line precharge voltage and a cell plate voltage.

9. The semiconductor memory device as recited in claim 7, wherein the mode controller includes:

a multiplexer for selectively outputting one of the plurality of control signals;

a plurality of control blocks for controlling the output of the multiplexer to provide a plurality of mode selection signals; and

a logic combining unit for logically combining the plurality of mode selection signals.

10. The semiconductor memory device as recited in claim 9, wherein the logical combining unit includes:

a NAND gate for NAND-operating the plurality of mode selection signals; and

an inverter for inverting an output of the NAND gate.

11. The semiconductor memory device as recited in claim 4, wherein the connection unit includes a MOS transistor that is arranged between the first power supply unit and the cell capacitor and receives the mode selection signal through a gate terminal.

12. The semiconductor memory device as recited in claim 11, wherein the MOS transistor is an NMOS transistor.

13. The semiconductor memory device as recited in claim 11, wherein the MOS transistor is a PMOS transistor.

14. The semiconductor memory device as recited in claim 11, wherein each of the plurality of reservoir capacitors is formed by using an electrode film and an insulating film used in a cell capacitor of unit cell arranged in a cell region of the semiconductor memory device.

15. The semiconductor memory device as recited in claim 14, wherein the reservoir capacitor is arranged in a peripheral region of the semiconductor memory device.