Feedback mechanism for flexible load balancing in a flow-based processor affinity scheme

• US 20070070904A1
• Filed: 09/26/2005
• Published: 03/29/2007
• Est. Priority Date: 09/26/2005
• Status: Abandoned Application

• Current Assignee: Erik Johnson, Stephen Goglin, Steven King
• Original Assignee: Erik Johnson, Stephen Goglin, Steven King
• Inventors: Johnson, Erik, King, Steven, Goglin, Stephen
• Application Number:
  US11/235,876
• Publication Number:
  US 20070070904A1
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: H04L 12/56 Packet switching systems

Abstract

In an embodiment, a method is provided. The method of this embodiment provides directing one or more packets to a first processor of a plurality of processors based, at least in part, on a flow associated with the one or more packets; and receiving from one of the plurality of processors a signal indicating a request to redirect one or more subsequent packets associated with the one processor to one or more other processors of the plurality of processors.

Claims

1. A method comprising:

directing one or more packets to a first processor of a plurality of processors based, at least in part, on a flow associated with the one or more packets; and

receiving from one of the plurality of processors a signal indicating a request to redirect one or more subsequent packets associated with the one processor to one or more other processors of the plurality of processors.

2. The method of claim 1, wherein each of the one or more subsequent packets is associated with a same flow.

3. The method of claim 1, wherein the signal is received from the first processor of the plurality of processors.

4. The method of claim 1, wherein the signal is received from one of the other processors of the plurality of processors.

5. The method of claim 4, wherein the one of the other processors comprises an underutilized processor.

6. An apparatus comprising:

a network controller to;

direct one or more packets to a first processor of a plurality of processors based, at least in part, on a flow associated with the one or more packets; and

receive from one of the plurality of processors a signal indicating a request to redirect one or more subsequent packets associated with the one processor to one or more other processors of the plurality of processors.

7. The apparatus of claim 6, wherein each of the one or more subsequent packets received on the network controller is associated with a same flow.

8. The apparatus of claim 6, wherein the network controller receives the signal from the first processor of the plurality of processors.

9. The apparatus of claim 6, wherein the network controller receives the signal from one of the other processors of the plurality of processors.

10. The apparatus of claim 9, wherein the one of the other processors comprises an underutilized processor.

11. A system comprising:

a plurality of processors;

a system bus communicatively coupled to the plurality of processors; and

a network controller communicatively coupled to the system bus operable to;

direct one or more packets to a first processor of the plurality of processors based, at least in part, on a flow associated with the one or more packets; and

receive from one of the plurality of processors a signal indicating a request to redirect one or more subsequent packets associated with the one processor to one or more other processors of the plurality of processors.

12. The system of claim 11, wherein each of the one or more subsequent packets is associated with a same flow.

13. The system of claim 11, wherein the signal is received from the first processor of the plurality of processors.

14. The system of claim 11, wherein the signal is received from one of the other processors of the plurality of processors.

15. The system of claim 14, wherein the one of the other processors comprises an underutilized processor.

16. An article of manufacture having stored thereon instructions, the instructions when executed by a machine, result in the following:

directing one or more packets to a first processor of a plurality of processors based, at least in part, on a flow associated with the one or more packets; and

receiving from one of the plurality of processors a signal indicating a request to redirect one or more subsequent packets associated with the one processor to one or more other processors of the plurality of processors.

17. The article of manufacture of claim 16, wherein each of the one or more subsequent packets is associated with a same flow.

18. The article of manufacture of claim 16, wherein the signal is received from the first processor of the plurality of processors.

19. The article of manufacture of claim 16, wherein the signal is received from one of the other processors of the plurality of processors.

20. The article of manufacture of claim 19, wherein the one of the other processors comprises an underutilized processor.