Data input device of semiconductor memory device
First Claim
1. A data input device of a semiconductor memory device, comprising:
- a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwidth to output an internal bandwidth signal;
a synchronization control part for generating synchronization signals and restrict-synchronization signals in synchronization with a data strobe signal, an activation of the restrict-synchronization signals being restricted through the internal bandwidth signal;
a first data input part for aligning the data in response to the synchronization signals; and
a second data input part for aligning the data in response to the restrict-synchronization signal and the internal bandwidth signal.
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Abstract
A data input device of a semiconductor memory device can reduce unnecessary current consumption occurring according to a setting of a bandwidth. The data input device includes: a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwidth to output an internal bandwidth signal; a synchronization control part for generating synchronization signals and restrict-synchronization signals in synchronization with a data strobe signal, an activation of the restrict-synchronization signals being restricted through the internal bandwidth signal; a first data input part for aligning the data in response to the synchronization signals; and a second data input part for aligning the data in response to the restrict-synchronization signal and the internal bandwidth signal.
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Citations
19 Claims
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1. A data input device of a semiconductor memory device, comprising:
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a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwidth to output an internal bandwidth signal;
a synchronization control part for generating synchronization signals and restrict-synchronization signals in synchronization with a data strobe signal, an activation of the restrict-synchronization signals being restricted through the internal bandwidth signal;
a first data input part for aligning the data in response to the synchronization signals; and
a second data input part for aligning the data in response to the restrict-synchronization signal and the internal bandwidth signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data input device for a semiconductor memory device, comprising:
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a first synchronization control part for generating synchronization signals synchronized with edges of a data strobe signal;
a second synchronization control part for generating restrict-synchronization signals synchronized with the edges of the data strobe signal in response to a bandwidth signal for setting a data bandwidth;
a first data input part for aligning data in response to the synchronization signals; and
a second data input part for aligning the data in response to the restrict-synchronization signal and an internal bandwidth signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification