FM TRANSMITTER

• US 20070071246A1
• Filed: 07/28/2006
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: RICOH Electronic Devices Co., Ltd. (Nisshinbo Holdings Incorporated)
• Original Assignee: Neuro Solution Corp.
• Inventors: MIYAGI, Hiroshi
• Granted Patent: US 7,920,835 B2
• Time in Patent Office: Days
• US Class Current: 381/15
• CPC Class Codes: H03C 3/40 using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
• CPC Class Codes: H04H 20/48 for FM stereophonic broadcast systems
• CPC Class Codes: H04H 20/72 of terrestrial networks
• CPC Class Codes: H04H 20/88 Stereophonic broadcast systems multiplex system in general H04J

Abstract

An object of the present invention is to provide an FM transmitter in which the degree of freedom in parts selection is improved. The FM transmitter comprises: an oscillator 72 connected with a crystal oscillator 70; a clock generating circuit 50 which uses a signal formed by frequency-dividing an output signal of the oscillator 72 as a reference frequency signal fr1, and which generates a clock signal having a frequency of an integer multiple of the frequency of the reference frequency signal fr1; a DSP 20 which operates synchronously with the clock signal to perform stereo modulation processing, FM modulation processing, and IQ modulation processing to inputted stereo data by digital processing; a frequency synthesizer 60 which uses a signal formed by frequency-dividing the output signal of the oscillator 72 as a reference frequency signal fr2, and which generates a signal having a frequency of an integer multiple of the frequency of the reference frequency signal fr2; mixers 40 and 42 which mix signals outputted from the DSP 20 with signals generated by the frequency synthesizer 60, respectively; an adder 44 which adds outputs of the mixers 40 and 42; and an amplifier 46 which amplifies an output signal of the adder 44 and transmits the amplified signal from an antenna 48.

Claims

1. An FM transmitter comprising:

an oscillator connected with a crystal oscillator;

a clock generating circuit which generates a clock signal synchronized with a signal formed by frequency-dividing an output signal of the oscillator;

a digital signal processor to which the clock signal generated by the clock generating circuit is inputted as an operating clock, and which performs a stereo modulating operation to stereo data by digital processing; and

a carrier wave generating circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted, and which generates a carrier wave synchronized with the inputted signal and having a frequency of an integer multiple of the frequency of the inputted signal,

the FM transmitter transmitting an FM modulation signal formed by frequency-modulating a stereo composite signal obtained by the stereo modulating operation performed by the digital signal processor.

2. The FM transmitter according to claim 1, wherein the clock generating circuit is a first PLL circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted as a first reference frequency signal fr1, and

wherein the clock signal having a frequency of m-fold of the frequency of the first reference frequency signal fr1 is generated when a division ratio of a first divider included in the first PLL circuit is set to an integer m.

3. The FM transmitter according to claim 2, wherein the carrier wave generating circuit is a second PLL circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted as a second reference frequency signal fr2, and

wherein the carrier wave having a frequency of n-fold of the frequency of the second reference frequency signal fr2 is generated when a division ratio of a second divider included in the second PLL circuit is set to an integer n.

4. The FM transmitter according to claim 1, wherein respective functions of the oscillator except the crystal oscillator, the clock generating circuit, the digital signal processor, and the carrier wave generating circuit are formed on one semiconductor substrate by using a semiconductor process.

5. The FM transmitter according to claim 2, wherein the second PLL circuit is a frequency synthesizer in which the division ratio n of the second frequency divider can be changed,

further comprising a control section which variably sets, by changing the division ratio n, a frequency of an output signal of the second PLL circuit at an assigned frequency interval of FM broadcast waves or at an integer fraction of the assigned frequency interval.

6. The FM transmitter according to claim 3, wherein the carrier wave generating circuit outputs, as the carrier wave, a signal formed by frequency-dividing a signal generated by the second PLL circuit, by a third frequency divider with a division ratio L.

7. The FM transmitter according to claim 6, wherein the second PLL circuit is a frequency synthesizer in which the division ratio n of the second frequency divider can be changed,

further comprising a control section which variably set, by changing the division ratio n, a frequency of an output signal of the second PLL circuit at an assigned frequency interval of FM broadcast waves or at a frequency interval set by multiplying an integer fraction of the assigned frequency interval by the division ratio L of the third frequency divider.

8. The FM transmitter according to claim 3, wherein the frequency of the second reference frequency signal fr2 is not coincident with an assigned frequency interval of FM broadcast waves or an integer fraction of the assigned frequency interval.

9. The FM transmitter according to claim 3, wherein the frequency of the second reference frequency signal fr2 is not coincident with an assigned frequency interval of FM broadcast waves or an integer fraction of the assigned frequency interval, and is not coincident with an integer multiple of 19 kHz.

10. The FM transmitter according to claim 6, wherein the frequency of the second reference frequency signal fr2 is not coincident with an assigned frequency interval of FM broadcast waves or a frequency set by multiplying an integer fraction of the assigned frequency interval by the division ratio L of the third frequency divider, and is not coincident with an integer multiple of 19 kHz.

11. The FM transmitter according to claim 8, wherein the crystal oscillator has a natural oscillation frequency of 32.768 kHz.

12. The FM transmitter according to claim 1, wherein a frequency of a second reference frequency signal fr2 is coincident with an assigned frequency interval of FM broadcast waves or an integer fraction of the assigned frequency interval.

13. The FM transmitter according to claim 6, wherein the frequency of the second reference frequency signal fr2 is coincident with an assigned frequency interval of FM broadcast waves or a frequency set by multiplying an integer fraction of the assigned frequency interval by the division ratio L of the third frequency divider.

14. The FM transmitter according to claim 1, wherein the digital signal processor performs an FM modulating operation to the stereo composite signal obtained by the stereo modulating operation, and performs an IQ modulating operation which extracts an I component and a Q component from the signal subjected to the FM modulating operation.

15. The FM transmitter according to claim 13, wherein the carrier wave generating circuit generates two kinds of the carrier waves which are 90°

out of phase from each other,

further comprising a transmitting circuit having two mixers which independently mix signals, each corresponding to each of an I component and a Q component that are extracted by the digital signal processor, with the two kinds of carrier waves that are generated by the carrier wave generating circuit, respectively, an adder which adds the two kinds of signals mixed by the two mixers, and an amplifier which amplifies an output signal of the adder and transmits the amplified signal from an antenna.

16. The FM transmitter according to claim 4, wherein the second PLL circuit has an oscillator whose oscillation frequency is changed in accordance with an amplitude of the stereo composite signal obtained by the stereo modulating operation performed by the digital signal processor.

17. The FM transmitter according to claim 1, wherein an external circuit is connected, instead of the oscillator connected with the crystal oscillator, and

wherein a signal supplied from the external circuit is used, instead of the output signal of the oscillator connected with the crystal oscillator.

18. The FM transmitter according to claim 4, wherein the semiconductor process is a CMOS process.

19. The FM transmitter according to claim 1, wherein the crystal oscillator has a natural oscillation frequency lower than 38 kHz.

20. An FM transmitter comprising:

an oscillator connected with a crystal oscillator;

a clock generating circuit which generates a clock signal synchronized with a signal formed by frequency-dividing an output signal of the oscillator;

a digital signal processor to which the clock signal generated by the clock generating circuit is inputted as an operating clock, and which performs a stereo modulating operation to stereo data by digital processing; and

a carrier wave generating circuit to which the output signal of the oscillator is directly inputted, and which generates a carrier wave that is synchronized with the output signal and that has a frequency of an integer multiple of the frequency of the output signal,

the FM transmitter transmitting an FM modulation signal formed by frequency-modulating a stereo composite signal obtained by the stereo modulating operation performed by the digital signal processor.

21. The FM transmitter according to claim 20, wherein the clock generating circuit is a first PLL circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted as a first reference frequency signal fr1, and

wherein the clock signal having a frequency of m-fold of the frequency of the first reference frequency signal fr1 is generated when a division ratio of a first divider included in the first PLL circuit is set to an integer m.

22. The FM transmitter according to claim 21, wherein the carrier wave generating circuit is a second PLL circuit to which the output signal of the oscillator is inputted as a second reference frequency signal fr2, and

wherein the carrier wave having a frequency of n-fold of the frequency of the second reference frequency signal fr2 is generated when a division ratio of a second divider included in the second PLL circuit is set to an integer n.

23. An FM transmitter comprising:

an oscillator connected with a crystal oscillator;

a clock generating circuit which generates a clock signal synchronized with an output signal of the oscillator;

a digital signal processor to which the clock signal generated by the clock generating circuit is inputted as an operating clock, and which performs a stereo modulating operation to stereo data by digital processing; and

a carrier wave generating circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted, and which generates a carrier wave synchronized with the inputted signal and having a frequency of an integer multiple of the frequency of the inputted signal,

the FM transmitter transmitting an FM modulation signal formed by frequency-modulating a stereo composite signal obtained by the stereo modulating operation performed by the digital signal processor.

24. The FM transmitter according to claim 23, wherein the clock generating circuit is a first PLL circuit to which the output signal of the oscillator is inputted as a first reference frequency signal fr1, and

wherein the clock signal having a frequency of m-fold of the frequency of the first reference frequency signal fr1 is generated when a division ratio of a first divider included in the first PLL circuit is set to an integer m.

25. The FM transmitter according to claim 24, wherein the carrier wave generating circuit is a second PLL circuit to which a signal formed by frequency-dividing the output signal of the oscillator is inputted as a second reference frequency signal fr2, and

wherein the carrier wave having a frequency of n-fold of the frequency of the second reference frequency signal fr2 is generated when a division ratio of a second divider included in the second PLL circuit is set to an integer n.