Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies
First Claim
1. A method for forming a CMOS semiconductor integrated circuit device comprising:
- providing a semiconductor substrate forming a dielectric layer overlying the semiconductor substrate;
forming a gate layer overlying the dielectric layer;
patterning the gate layer to form a gate structure including edges;
forming a dielectric layer overlying the gate structure to protect the gate structure including the edges, the dielectric layer having a thickness of less than 1000 A nanometers;
patterning the dielectric layer overlying the gate structure;
etching a source region and a drain region adjacent to the gate structure using the patterned dielectric layer as a protective layer;
depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region; and
causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region.
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Accused Products
Abstract
A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.
159 Citations
36 Claims
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1. A method for forming a CMOS semiconductor integrated circuit device comprising:
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providing a semiconductor substrate forming a dielectric layer overlying the semiconductor substrate;
forming a gate layer overlying the dielectric layer;
patterning the gate layer to form a gate structure including edges;
forming a dielectric layer overlying the gate structure to protect the gate structure including the edges, the dielectric layer having a thickness of less than 1000 A nanometers;
patterning the dielectric layer overlying the gate structure;
etching a source region and a drain region adjacent to the gate structure using the patterned dielectric layer as a protective layer;
depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region; and
causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A CMOS semiconductor integrated circuit device, the device comprising:
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an NMOS device comprising a gate region, a source region, and a drain region;
an NMOS channel region formed between the source region and drain region;
a silicon carbide material formed within the source region and formed within the drain region;
whereupon the silicon carbide material causes the channel region to be in a tensile mode; and
a PMOS device comprising a gate region, a source region, and a drain region;
a PMOS channel region formed between the source region and the drain region;
a silicon germanium formed within the source region and formed with in the drain region; and
whereupon the silicon germanium material causes the channel region to be in a compressive mode. - View Dependent Claims (12, 13, 14, 15, 17, 18, 19, 20)
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16. The device of claim II wherein the silicon germanium material is single crystal material.
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21. A method for forming a CMOS integrated circuit device, the method comprising:
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providing a semiconductor substrate;
forming a gate layer overlying the semiconductor substrate;
patterning the gate layer to form an NMOS gate structure including edges and a PMOS gate structure including edges;
forming a dielectric layer overlying the NMOS gate structure to protect the NMOS gate structure including the edges and overlying the PMOS gate structure to protect the PMOS gate structure including the edges;
simultaneously etching a first source region and a first drain region adjacent to the NMOS gate structure and second source region and second drain region adjacent to the PMOS gate structure using the dielectric layer as a protective layer;
depositing silicon germanium material into the first source region and the first drain region to cause a channel region between the first source region and the first drain region of the NMOS gate structure to be strained in a compressive mode;
depositing silicon carbide material into the second source region and second drain region to cause the channel region between the second source region and the second drain region of the PMOS gate structure to be strained in a tensile mode. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A PMOS integrated circuit device, the device comprising:
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a semiconductor substrate comprising a surface region;
an isolation region formed within the semiconductor substrate;
a gate dielectric layer overlying the surface region of the semiconductor substrate;
a PMOS gate layer, the PMOS gate layer including a first edge and a second edge;
a first lightly doped region formed within a vicinity of the first edge;
a second lightly doped region formed within a vicinity of the second edge;
a first sidewall spacer formed on the first edge and on a portion of the first lightly doped region;
a second sidewall spacer formed on the second edge and on a portion of the second lightly doped region;
a first etched region of semiconductor substrate formed adjacent to the first sidewall spacer;
a second etched region of semiconductor substrate formed adjacent to the second sidewall spacer;
a first silicon germanium material formed within the first etched region to form a first source/drain region;
a second silicon germanium material formed within the second etched region to form a second source/drain region; and
a PMOS channel region formed between the first silicon germanium material and the second silicon germanium layer. - View Dependent Claims (36)
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Specification