Method of sealing two plates with the formation of an ohmic contact therebetween

• US 20070072391A1
• Filed: 12/21/2004
• Published: 03/29/2007
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Pocas, Stephane, Moriceau, Hubert, Michaud, Jean-Francois
• Granted Patent: US 8,975,156 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence

Abstract

The invention relates to a sealing process for two wafers (2, 12) made of semiconducting materials, comprising:

• • a step for implantation of metallic species (4) in at least the first wafer, a step for assembly of the first and second wafer, an annealing step.

Claims

1-26. -26. (canceled)

27. Sealing processing for two wafers made of semiconducting materials, comprising:

a step for implantation of metallic species in at least the first wafer,

a step for assembly of the first and second wafer by molecular bonding,

a step for formation of metallic compounds, alloys between the implanted metallic species and the semiconducting materials of the two wafers, said metallic compound forming a resistive contact between the two wafers, at the assembly interface.

28. Process according to claim 27, the formation step of the metallic compounds resulting from a heat treatment at a temperature equal at least to the formation temperature of the said compounds.

29. Process according to claim 27, the metallic species being implanted at a depth (Rp) of between 5 nm and 20 nm under the surface of the implanted wafer.

30. Process according to claim 27, the metallic species being implanted at a dose of between 10¹⁴ and a few 10¹⁸ species/cm².

31. Process according to claim 27, also comprising an amorphisation step before assembly to make all or part of the surface layer of the first wafer amorphous.

32. Process according to claim 31, the amorphisation step comprising deposition of an amorphous material layer before and/or after implantation of metallic species.

33. Process according to claim 31, the amorphisation step comprising a surface implantation, for example by hydrogen or metallic species.

34. Process according to claim 27, each of the wafers being made from a material chosen from among silicon, gallium arsenide (GaAs), SiC (silicon carbide), InP (Indium phosphide), Germanium (Ge), le silicon-Germanium (SiGe).

35. Process according to claim 27, the implanted species being Nickel and/or palladium and/or Cobalt, and/or Platinum, and/or Tantalum, and/or Tungsten, and/or Titanium, and/or Copper.

36. Process according to claim 27, at least one of the wafers being a heterostructure, for example of the SOI type.

37. Process according to claim 27, at least one of the wafers being thinned, after assembly or after the formation step of metallic compounds.

38. Process according to claim 27, at least one of the wafers being a debondable structure.

39. Process according to claim 27, at least one of the wafers comprising a weakening plane.

40. Process according to claim 27, the wafer comprising a weakening plane being thinned by fracture along the said weakening plane, after assembly or after the formation step of the metallic compounds.

41. Process according to claim 27, at least one of the wafers comprising at least one circuit or circuits layer, on or close to its face to be assembled.

42. Process according to claim 27, the implantation step of metallic species being done through a mask to obtain local implantation zones.

43. Process according to claim 27, also comprising the formation of an insulating layer on the first wafer, before it is implanted with metallic species.

44. Process according to claim 27, also comprising a thinning step of the implanted wafer after implantation of metallic species.

45. Process according to claim 27, the first wafer comprising at least one insulating zone located at the surface so as to obtain local implantation zones.

58. Structure obtained by a process according to claim 27, comprising two substrates made of semiconducting materials assembled by molecular bonding and having localised zones of metallic compounds at the assembly interface, these metallic compounds being alloys made from semiconducting materials of substrates at the assembly interface and at least one metal chosen from among nickel, palladium, cobalt, platinum, tantalum, titanium, copper.

59. Structure according to claim 58, the semiconducting materials being chosen from among Si, GaAs, SiC, InP, SiGe.

60. Structure according to claim 58, at least one of the substrates being a heterostructure.

61. Structure according to claim 58, at least one of the substrates being a thin film.

62. Structure according to claim 58, at least one of the substrates comprising electronic and/or optical and/or mechanical components.

63. Structure according to claim 58, one of the substrates being a thin film made of silicon comprising RF circuits.

64. Structure according to claim 63, the other substrate being made of high resistivity silicon.

46. Structure comprising two substrates made of semiconducting materials assembled by molecular bonding and having localised zones of metallic compounds at the assembly interface, these metallic compounds being alloys made from semiconducting materials of substrates at the assembly interface and at least one metal chosen from among nickel, palladium, cobalt, platinum, tantalum, tungsten, titanium, copper.

47. Structure according to claim 46, the semiconducting materials being chosen from among Si, GaAs, SiC, InP, SiGe.

48. Structure according to claim 46, at least one of the substrates being a heterostructure.

49. Structure according to claim 46, at least one of the substrates being a thin film.

50. Structure according to claim 46, at least one of the substrates comprising electronic and/or optical and/or mechanical components.

51. Structure according to claim 46, one of the substrates being a thin film made of silicon comprising RF circuits.

52. Structure according to claim 51, the other substrate being made of high resistivity silicon.

53. Sealing processing for two wafers made of semiconducting materials, comprising:

a step for implantation of metallic species in at least the first wafer, at a depth (Rp) of between 5 nm and 20 nm under the surface of said first wafer, at a dose of between 10¹⁴ and a few 10¹⁸ species/cm²,

a step for assembly of the first and second wafer by molecular bonding,

a step for formation of metallic compounds, alloys between the implanted metallic species and the semiconducting materials of the two wafers, said metallic compound forming a resistive contact between the two wafers, at the assembly interface.

54. Process according to claim 53, the formation step of the metallic compounds resulting from a heat treatment at a temperature equal at least to the formation temperature of the said compounds.

55. Process according to claim 53, also comprising an amorphisation step before assembly to make all or part of the surface layer of the first wafer amorphous.

56. Process according to claim 55, the amorphisation step comprising deposition of an amorphous material layer before and/or after implantation of metallic species.

57. Process according to claim 55, the amorphisation step comprising a surface implantation, for example by hydrogen or metallic species.