Fabrication Method of Semiconductor Integrated Circuit Device

• US 20070072408A1
• Filed: 09/13/2006
• Published: 03/29/2007
• Est. Priority Date: 08/07/2001
• Status: Abandoned Application

• Current Assignee: Atsushi Maekawa, Hiroyuki Enomoto, Kazutami Tago
• Original Assignee: Atsushi Maekawa, Hiroyuki Enomoto, Kazutami Tago
• Inventors: Maekawa, Atsushi, Tago, Kazutami, Enomoto, Hiroyuki
• Application Number:
  US11/531,611
• Publication Number:
  US 20070072408A1
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76832 Multiple layers

Abstract

The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched. When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF₆ and NH₃ is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves.

Claims

1-17. -17. (canceled)

18. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the conductive layer; and

(c) using a mixed gas of CHF₃ and N₂ to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

19. The process according to claim 18, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.1 to 1/200.

20. The process according to claim 18, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.2 to 1/20.

21. The process according to claim 18, wherein in the mixed gas, the flow ratio of CHF₃ to N₂ ranges from 1/0.5 to 1/10.

22. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide, silicon carbonitride or silicon carboxide as a main component over the conductive layer; and

(c) using a mixed gas including at least one of CHF₃ and CF₄, and N₂, which does not contain oxygen, to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

23-29. -29. (canceled)

30. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon nitride as a main component over the conductive layer; and

(c) using a mixed gas including at least one of CHF₃ and CF₄, and N₂, which does not contain oxygen, to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.