Latch-up free vertical TVS diode array structure using trench isolation

• US 20070073807A1
• Filed: 11/30/2006
• Published: 03/29/2007
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur
• Granted Patent: US 7,880,223 B2
• Time in Patent Office: Days
• US Class Current: 709/203
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode

Abstract

A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

Claims

1. A transient voltage suppressing (TVS) array comprising:

a plurality of diodes formed as dopant regions of different conductivity types for constituting PN junctions in a semiconductor substrate; and

an isolation trench disposed between said diodes for isolating and preventing a parasitic PNP or NPN transistor to a latch-up between said doped regions in said semiconductor substrate of different conductivity types.

2. The TVS array of claim 1 wherein:

said PN junctions are formed as vertical PN junctions in said semiconductor substrate with electrodes of a first and a second electrical conductivity types to connect respectively to a high and low voltages disposed separately on a top surface and a bottom surface of said semiconductor substrate.

3. The TVS array of claim 1 further comprising:

at least two vertically stacked PN junctions disposed between two of said isolation trenches having a greater lateral width in said semiconductor substrate for constituting a Zener diode.

4. The TVS array of claim 3 wherein:

said Zener diode is further isolated by two of isolation trenches disposed immediately next to and isolating said Zener diode from another of said diodes of said TVS array whereby said latch-up is prevented.

5. The TVS array of claim 1 further comprising:

at least two input/output (I/O) contact pads, each contacting two PN junctions functioning respectively as a high-side diode and a low-side diode and insulated by an isolation trench with each of said I/O contact pads overlying an insulation layer covering said isolation trench.

6. The TVS array of claim 1 wherein:

said semiconductor substrate further comprising a N-type substrate supporting a N-type epitaxial layer wherein said PN junctions are formed as vertical PN junctions in said semiconductor substrate with an anode electrode disposed on a bottom surface of said substrate for connecting to a high voltage and a cathode electrode disposed on a top surface of said substrate for connecting to a low voltage.

7. The TVS array of claim 6 wherein:

said semiconductor substrate further comprising a P-body region disposed between two of said isolation trenches in said N-type epitaxial layer wherein said body region further encompassing a Zener N-doped region to form a vertically stacked PN junctions constituting a Zener diode between two of said isolation trenches.

8. The TVS array of claim 6 wherein:

said semiconductor substrate further comprising a P-body region disposed between two of said isolation trenches in said N-type epitaxial layer wherein said body region further encompassing a N-doped region to form a PN junction with said P-body to function as a low side diode of said TVS array

9. A transient voltage suppressing (TVS) array disposed on a semiconductor substrate supporting an epitaxial layer of a first conductivity type wherein said TVS array further comprising:

a plurality of isolation trenches opened in said epitaxial layer with a body region of a second conductivity type in said epitaxial layer between two of said trenches; and

a Zener doped region in said body region of said first conductivity type for constituting a Zener diode comprising vertically stacked PN junctions for carrying a transient current for suppressing a transient voltage.

10. The TVS array of claim 9 wherein:

said Zener diode is further isolated by two of isolation trenches disposed immediately next to said Zener diode for isolating said Zener diode from another PN junction of said TVS array whereby a latch-up is prevented.

11. The TVS array of claim 9 wherein:

said body region further comprising a low-side diode doped region of said first conductivity type for constituting a low side diode; and

said epitaxial layer further comprising a doped region of said second conductivity type forming a PN junction with said epitaxial layer for constituting a high-side diode for electrically connecting to said low-side diode through an input-output (I/O) contact pad.

12. The TVS array of claim 9 wherein:

said epitaxial layer further comprising vertical PN junctions constituting diodes therein and electrically connecting to electrodes of a first and a second electrical conductivity types for connecting respectively to a high and low voltages disposed separately on a top surface and a bottom surface of said semiconductor substrate.

13. The TVS array of claim 9 wherein:

said semiconductor substrate further comprising a N-type substrate supporting a N-type epitaxial layer to form a plurality of PN junctions in said N-type epitaxial layer as vertical PN junctions in said semiconductor substrate with an anode electrode disposed on a bottom surface of said substrate for connecting to a high voltage and a cathode electrode disposed on a top surface of said substrate for connecting to a low voltage.

14. The TVS array of claim 13 wherein:

said body region is a P-body region disposed between two of said isolation trenches in said N-type epitaxial layer wherein said body region further encompassing a Zener N-doped region to form a vertically stacked PN junctions constituting a Zener diode between two of said isolation trenches.

15. The TVS array of claim 13 wherein:

said body region is a P-body region disposed between two of said isolation trenches in said N-type epitaxial layer wherein said body region further encompassing a N-doped region to form a PN junction with said P-body to function as a low side diode of said TVS array

16. A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device, the method comprising:

opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of said isolation trenches; and

applying an source mask for implanting a plurality of doped regions of said first conductivity type constituting a plurality of diodes wherein said isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between said doped regions of different conductivity types.

17. The method of claim 16 further comprising:

applying a contact mask for implanting doped regions of said second conductivity type away from said body region for constituting high side diodes with said epitaxial layer to connect to said low side diodes encompassed in said body region with input-output (IO) contact pads across said isolation trenches.

18. The method of claim 16 wherein:

said step implanting a plurality of doped regions of said first conductivity type constituting a plurality of diodes in said step further comprising a step of forming a Zener doped region with a greater width wherein said Zener doped region comprising vertically stacked PN junctions for functioning as a Zener diode with said body region in said epitaxial layer.

19. The method of claim 18 wherein:

said step opening a plurality of isolation trenches further comprising a step of opening isolation trenches immediately next to said Zener diode for isolating said Zener diode for preventing said latch-up between said doped regions of different conductivity types.

20. The method of claim 16 further comprising:

depositing a metal layer on a bottom surface of said substrate to function as an electrode for said TVS array.

21. The method of claim 16 further comprising:

depositing a metal layer on a to surface of said substrate and patterning said metal layer to function as input-output contact pads and as an electrode for said TVS array of an opposite conductivity from an electrode formed on said bottom surface of said semiconductor substrate.